Lines Matching +full:timing +full:- +full:0

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Masahiro Yamada <yamada.masahiro@socionext.com>
15       - enum:
16           - amd,pensando-elba-sd4hc
17           - microchip,mpfs-sd4hc
18           - socionext,uniphier-sd4hc
19       - const: cdns,sd4hc
36   # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
39   cdns,phy-input-delay-sd-highspeed:
40     description: Value of the delay in the input path for SD high-speed timing
42     minimum: 0
43     maximum: 0x1f
45   cdns,phy-input-delay-legacy:
46     description: Value of the delay in the input path for legacy timing
48     minimum: 0
49     maximum: 0x1f
51   cdns,phy-input-delay-sd-uhs-sdr12:
52     description: Value of the delay in the input path for SD UHS SDR12 timing
54     minimum: 0
55     maximum: 0x1f
57   cdns,phy-input-delay-sd-uhs-sdr25:
58     description: Value of the delay in the input path for SD UHS SDR25 timing
60     minimum: 0
61     maximum: 0x1f
63   cdns,phy-input-delay-sd-uhs-sdr50:
64     description: Value of the delay in the input path for SD UHS SDR50 timing
66     minimum: 0
67     maximum: 0x1f
69   cdns,phy-input-delay-sd-uhs-ddr50:
70     description: Value of the delay in the input path for SD UHS DDR50 timing
72     minimum: 0
73     maximum: 0x1f
75   cdns,phy-input-delay-mmc-highspeed:
76     description: Value of the delay in the input path for MMC high-speed timing
78     minimum: 0
79     maximum: 0x1f
81   cdns,phy-input-delay-mmc-ddr:
82     description: Value of the delay in the input path for eMMC high-speed DDR timing
89     minimum: 0
90     maximum: 0x1f
92   cdns,phy-dll-delay-sdclk:
97     minimum: 0
98     maximum: 0x7f
100   cdns,phy-dll-delay-sdclk-hsmmc:
105     minimum: 0
106     maximum: 0x7f
108   cdns,phy-dll-delay-strobe:
113     minimum: 0
114     maximum: 0x7f
117   - compatible
118   - reg
119   - interrupts
120   - clocks
123   - $ref: mmc-controller.yaml
124   - if:
128             const: amd,pensando-elba-sd4hc
133             - description: Host controller registers
134             - description: Elba byte-lane enable register for writes
136         - resets
145   - |
147         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
148         reg = <0x5a000000 0x400>;
149         interrupts = <0 78 4>;
151         bus-width = <8>;
152         mmc-ddr-1_8v;
153         mmc-hs200-1_8v;
154         mmc-hs400-1_8v;
155         cdns,phy-dll-delay-sdclk = <0>;