Lines Matching +full:input +full:- +full:value
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
34 # PHY DLL input delays:
39 cdns,phy-input-delay-sd-highspeed:
40 description: Value of the delay in the input path for SD high-speed timing
45 cdns,phy-input-delay-legacy:
46 description: Value of the delay in the input path for legacy timing
51 cdns,phy-input-delay-sd-uhs-sdr12:
52 description: Value of the delay in the input path for SD UHS SDR12 timing
57 cdns,phy-input-delay-sd-uhs-sdr25:
58 description: Value of the delay in the input path for SD UHS SDR25 timing
63 cdns,phy-input-delay-sd-uhs-sdr50:
64 description: Value of the delay in the input path for SD UHS SDR50 timing
69 cdns,phy-input-delay-sd-uhs-ddr50:
70 description: Value of the delay in the input path for SD UHS DDR50 timing
75 cdns,phy-input-delay-mmc-highspeed:
76 description: Value of the delay in the input path for MMC high-speed timing
81 cdns,phy-input-delay-mmc-ddr:
82 description: Value of the delay in the input path for eMMC high-speed DDR timing
86 # The approximate delay value will be
87 # (<delay property value>/128)*sdmclk_clock_period.
92 cdns,phy-dll-delay-sdclk:
94 Value of the delay introduced on the sdclk output for all modes except
100 cdns,phy-dll-delay-sdclk-hsmmc:
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
108 cdns,phy-dll-delay-strobe:
110 Value of the delay introduced on the dat_strobe input used in
117 - compatible
118 - reg
119 - interrupts
120 - clocks
123 - $ref: mmc-controller.yaml
124 - if:
128 const: amd,pensando-elba-sd4hc
133 - description: Host controller registers
134 - description: Elba byte-lane enable register for writes
136 - resets
145 - |
147 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
151 bus-width = <8>;
152 mmc-ddr-1_8v;
153 mmc-hs200-1_8v;
154 mmc-hs400-1_8v;
155 cdns,phy-dll-delay-sdclk = <0>;