Lines Matching +full:keembay +full:- +full:emmc +full:- +full:phy
3 The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
7 [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
9 [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
12 - compatible: Compatibility string. One of:
13 - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
14 - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
15 - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
16 - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
17 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
18 - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
19 For this device it is strongly suggested to include clock-output-names and
20 #clock-cells.
21 - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY
22 For this device it is strongly suggested to include clock-output-names and
23 #clock-cells.
24 - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
26 - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
27 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
28 - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
29 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
30 - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
31 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
32 - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
33 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
34 - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
35 For this device it is strongly suggested to include arasan,soc-ctl-syscon.
37 [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
39 - reg: From mmc bindings: Register location and length.
40 - clocks: From clock bindings: Handles to clock inputs.
41 - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
42 - interrupts: Interrupt specifier
44 Required Properties for "arasan,sdhci-5.1":
45 - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
46 - phy-names: MUST be "phy_arasan".
49 - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
52 - clock-output-names: If specified, this will be the name of the card clock
53 which will be exposed by this device. Required if #clock-cells is
55 - #clock-cells: If specified this should be the value <0> or <1>. With this
57 Clock. These clocks are expected to be consumed by our PHY.
58 - xlnx,fails-without-test-cd: when present, the controller doesn't work when
61 - xlnx,int-clock-stable-broken: when present, the controller always reports
64 - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
70 compatible = "arasan,sdhci-8.9a";
72 clock-names = "clk_xin", "clk_ahb";
74 interrupt-parent = <&gic>;
79 compatible = "arasan,sdhci-5.1";
81 clock-names = "clk_xin", "clk_ahb";
83 interrupt-parent = <&gic>;
86 phy-names = "phy_arasan";
90 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
94 clock-names = "clk_xin", "clk_ahb";
95 arasan,soc-ctl-syscon = <&grf>;
96 assigned-clocks = <&cru SCLK_EMMC>;
97 assigned-clock-rates = <200000000>;
98 clock-output-names = "emmc_cardclock";
100 phy-names = "phy_arasan";
101 #clock-cells = <0>;
105 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
106 interrupt-parent = <&gic>;
110 clock-names = "clk_xin", "clk_ahb";
111 clock-output-names = "clk_out_sd0", "clk_in_sd0";
112 #clock-cells = <1>;
113 clk-phase-sd-hs = <63>, <72>;
117 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
118 interrupt-parent = <&gic>;
122 clock-names = "clk_xin", "clk_ahb";
123 clock-output-names = "clk_out_sd0", "clk_in_sd0";
124 #clock-cells = <1>;
125 clk-phase-sd-hs = <132>, <60>;
128 emmc: sdhci@ec700000 {
129 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
131 interrupt-parent = <&ioapic1>;
135 clock-names = "clk_xin", "clk_ahb", "gate";
136 clock-output-names = "emmc_cardclock";
137 #clock-cells = <0>;
139 phy-names = "phy_arasan";
140 arasan,soc-ctl-syscon = <&sysconf>;
144 compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc";
146 interrupt-parent = <&ioapic1>;
150 clock-names = "clk_xin", "clk_ahb", "gate";
151 clock-output-names = "sdxc_cardclock";
152 #clock-cells = <0>;
154 phy-names = "phy_arasan";
155 arasan,soc-ctl-syscon = <&sysconf>;
159 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
162 clock-names = "clk_xin", "clk_ahb";
166 phy-names = "phy_arasan";
167 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
168 assigned-clock-rates = <200000000>;
169 clock-output-names = "emmc_cardclock";
170 #clock-cells = <0>;
171 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
175 compatible = "intel,keembay-sdhci-5.1-sd";
178 clock-names = "clk_xin", "clk_ahb";
181 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
185 compatible = "intel,keembay-sdhci-5.1-sdio";
188 clock-names = "clk_xin", "clk_ahb";
191 arasan,soc-ctl-syscon = <&sd1_phy_syscon>;