Lines Matching +full:axg +full:- +full:clkc
10 - compatible : contains one of:
11 - "amlogic,meson-gx-mmc"
12 - "amlogic,meson-gxbb-mmc"
13 - "amlogic,meson-gxl-mmc"
14 - "amlogic,meson-gxm-mmc"
15 - "amlogic,meson-axg-mmc"
16 - clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
17 - clock-names: Should contain the following:
18 "core" - Main peripheral bus clock
19 "clkin0" - Parent clock of internal mux
20 "clkin1" - Other parent clock of internal mux
23 - resets : phandle of the internal reset line
26 - amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
32 compatible = "amlogic,meson-gxbb-mmc";
35 clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
36 clock-names = "core", "clkin0", "clkin1";
37 pinctrl-0 = <&emmc_pins>;