Lines Matching +full:ast2500 +full:- +full:lhc
5 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth
11 The LPC controller is represented as a multi-function device to account for the
18 APB-to-LPC bridging amonst other functions.
21 as LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
33 [1] https://www.renesas.com/en-sg/doc/products/mpumcu/001/rej09b0078_h8s2168.pdf?key=7c888374547021…
34 …el.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev…
40 - compatible: One of:
41 "aspeed,ast2400-lpc-v2", "simple-mfd", "syscon"
42 "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"
43 "aspeed,ast2600-lpc-v2", "simple-mfd", "syscon"
45 - reg: contains the physical address and length values of the Aspeed
48 - #address-cells: <1>
49 - #size-cells: <1>
50 - ranges: Maps 0 to the physical address and length of the LPC memory
56 compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon";
59 #address-cells = <1>;
60 #size-cells = <1>;
63 lpc_snoop: lpc-snoop@0 {
64 compatible = "aspeed,ast2600-lpc-snoop";
67 snoop-ports = <0x80>;
73 -------------------
76 LPC firmware hub cycles, configuration of the LPC-to-AHB mapping, UART
81 - compatible: One of:
82 "aspeed,ast2400-lpc-ctrl";
83 "aspeed,ast2500-lpc-ctrl";
84 "aspeed,ast2600-lpc-ctrl";
86 - reg: contains offset/length values of the host interface controller
89 - clocks: contains a phandle to the syscon node describing the clocks.
94 - memory-region: A phandle to a reserved_memory region to be used for the LPC
97 - flash: A phandle to the SPI flash controller containing the flash to
102 lpc_ctrl: lpc-ctrl@80 {
103 compatible = "aspeed,ast2500-lpc-ctrl";
106 memory-region = <&flash_memory>;
111 -------------------
120 - compatible: One of:
121 "aspeed,ast2400-lhc";
122 "aspeed,ast2500-lhc";
123 "aspeed,ast2600-lhc";
125 - reg: contains offset/length values of the LHC memory regions. In the
126 AST2400 and AST2500 there are two regions.
130 lhc: lhc@a0 {
131 compatible = "aspeed,ast2500-lhc";
136 -----------------
143 - compatible: One of:
144 "aspeed,ast2600-lpc-reset";
145 "aspeed,ast2500-lpc-reset";
146 "aspeed,ast2400-lpc-reset";
148 - reg: offset and length of the IP in the LHC memory region
149 - #reset-controller indicates the number of reset cells expected
153 lpc_reset: reset-controller@98 {
154 compatible = "aspeed,ast2500-lpc-reset";
156 #reset-cells = <1>;