Lines Matching +full:half +full:- +full:bus
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Manish Narani <manish.narani@xilinx.com>
12 - Michal Simek <michal.simek@xilinx.com>
15 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
16 32-bit bus width configurations.
18 The Zynq DDR ECC controller has an optional ECC support in half-bus width
19 (16-bit) configuration.
27 - snps,ddrc-3.80a
28 - xlnx,zynq-ddrc-a05
29 - xlnx,zynqmp-ddrc-2.40a
38 - compatible
39 - reg
42 - if:
47 - snps,ddrc-3.80a
48 - xlnx,zynqmp-ddrc-2.40a
51 - interrupts
59 - |
60 memory-controller@f8006000 {
61 compatible = "xlnx,zynq-ddrc-a05";
65 - |
67 #address-cells = <2>;
68 #size-cells = <2>;
70 memory-controller@fd070000 {
71 compatible = "xlnx,zynqmp-ddrc-2.40a";
73 interrupt-parent = <&gic>;