Lines Matching +full:low +full:- +full:latency

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Christophe Kerello <christophe.kerello@foss.st.com>
11   - Marek Vasut <marex@denx.de>
14   st,fmc2-ebi-cs-transaction-type:
33   st,fmc2-ebi-cs-cclk-enable:
40   st,fmc2-ebi-cs-mux-enable:
46   st,fmc2-ebi-cs-buswidth:
52   st,fmc2-ebi-cs-waitpol-high:
54       By default, NWAIT is active low.
57   st,fmc2-ebi-cs-waitcfg-enable:
64   st,fmc2-ebi-cs-wait-enable:
66       account after the programmed latency period to insert wait states
70   st,fmc2-ebi-cs-asyncwait-enable:
76   st,fmc2-ebi-cs-cpsize:
84   st,fmc2-ebi-cs-byte-lane-setup-ns:
86       defined in nanoseconds from NBLx low to Chip Select NEx low.
88   st,fmc2-ebi-cs-address-setup-ns:
92   st,fmc2-ebi-cs-address-hold-ns:
97   st,fmc2-ebi-cs-data-setup-ns:
101   st,fmc2-ebi-cs-bus-turnaround-ns:
105   st,fmc2-ebi-cs-data-hold-ns:
109   st,fmc2-ebi-cs-clk-period-ns:
113   st,fmc2-ebi-cs-data-latency-ns:
114     description: This property defines the data latency before reading or
117   st,fmc2-ebi-cs-write-address-setup-ns:
121   st,fmc2-ebi-cs-write-address-hold-ns:
126   st,fmc2-ebi-cs-write-data-setup-ns:
130   st,fmc2-ebi-cs-write-bus-turnaround-ns:
134   st,fmc2-ebi-cs-write-data-hold-ns:
138   st,fmc2-ebi-cs-max-low-pulse-ns:
139     description: This property defines the maximum chip select low pulse