Lines Matching +full:2 +full:ns

19  - #address-cells:	Must be set to 2 to allow memory address translation
41 2 - GPMC_WAIT0 pin edge
43 - interrupt-cells: Must be set to 2
47 - gpio-cells: Must be set to 2
58 - gpmc,cs-on-ns: Assertion time
59 - gpmc,cs-rd-off-ns: Read deassertion time
60 - gpmc,cs-wr-off-ns: Write deassertion time
63 - gpmc,adv-on-ns: Assertion time
64 - gpmc,adv-rd-off-ns: Read deassertion time
65 - gpmc,adv-wr-off-ns: Write deassertion time
66 - gpmc,adv-aad-mux-on-ns: Assertion time for AAD
67 - gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
68 - gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
71 - gpmc,we-on-ns Assertion time
72 - gpmc,we-off-ns: Deassertion time
75 - gpmc,oe-on-ns: Assertion time
76 - gpmc,oe-off-ns: Deassertion time
77 - gpmc,oe-aad-mux-on-ns: Assertion time for AAD
78 - gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
82 - gpmc,page-burst-access-ns: Multiple access word delay
83 - gpmc,access-ns: Start-cycle to first data valid delay
84 - gpmc,rd-cycle-ns: Total read cycle time
85 - gpmc,wr-cycle-ns: Total write cycle time
86 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
87 - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
88 - gpmc,clk-activation-ns: GPMC clock activation time
89 - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
102 - gpmc,time-para-granularity: Multiply all access times by 2
105 - gpmc,wr-access-ns: In synchronous write mode, for single or
110 - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
123 1 or 2.
126 multiplexing mode and 2 for address-data
147 gpmc,num-waitpins = <2>;
148 #address-cells = <2>;
152 #interrupt-cells = <2>;
154 #gpio-cells = <2>;