Lines Matching +full:opp +full:- +full:specific
4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
15 - nvidia,memory-controller : Phandle of the Memory Controller node.
16 - #interconnect-cells : Should be 0.
17 - operating-points-v2: See ../bindings/opp/opp.txt for details.
19 For each opp entry in 'operating-points-v2' table:
20 - opp-supported-hw: One bitfield indicating SoC process ID mask
23 matches, the OPP gets enabled.
26 - power-domains: Phandle of the SoC "core" power domain.
32 opp_table: opp-table {
33 compatible = "operating-points-v2";
35 opp@36000000 {
36 opp-microvolt = <950000 950000 1300000>;
37 opp-hz = /bits/ 64 <36000000>;
42 memory-controller@7000f400 {
43 #address-cells = < 1 >;
44 #size-cells = < 0 >;
45 #interconnect-cells = <0>;
46 compatible = "nvidia,tegra20-emc";
50 nvidia,memory-controller = <&mc>;
51 power-domains = <&domain>;
52 operating-points-v2 = <&opp_table>;
56 Embedded Memory Controller ram-code table
58 If the emc node has the nvidia,use-ram-code property present, then the
60 apply for which ram-code settings.
62 If the emc node lacks the nvidia,use-ram-code property, this level is omitted
67 - name : Should be emc-tables
68 - nvidia,ram-code : the binary representation of the ram-code board strappings
84 this information based on the specific system information and just
90 on a 2-pin "ram code" bootstrap setting on the board. The values of
95 - name : Should be emc-table
96 - compatible : Should contain "nvidia,tegra20-emc-table".
97 - reg : either an opaque enumerator to tell different tables apart, or
99 - clock-frequency : the clock frequency for the EMC at which this
101 - nvidia,emc-registers : a 46 word array of EMC registers to be programmed
102 for operation at the 'clock-frequency' setting.
112 emc-table@166000 {
114 compatible = "nvidia,tegra20-emc-table";
115 clock-frequency = < 166000 >;
116 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
122 emc-table@333000 {
124 compatible = "nvidia,tegra20-emc-table";
125 clock-frequency = < 333000 >;
126 nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0