Lines Matching +full:exynos4 +full:- +full:sysreg
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
17 CSIS, FIMC-LITE and FIMC-IS (ISP).
25 '#address-cells':
28 '#size-cells':
31 '#clock-cells':
41 clock-names:
44 - const: sclk_cam0
45 - const: sclk_cam1
46 - const: pxl_async0
47 - const: pxl_async1
49 clock-output-names:
52 parallel-ports:
59 $ref: /schemas/graph.yaml#/$defs/port-base
66 $ref: /schemas/media/video-interfaces.yaml#
69 pinctrl-names:
72 - const: default
73 - const: idle
74 - const: active_a
75 - const: active_b
78 "^csis@[0-9a-f]+$":
80 $ref: samsung,exynos4210-csis.yaml#
81 description: MIPI CSI-2 receiver.
83 "^fimc@[0-9a-f]+$":
85 $ref: samsung,exynos4210-fimc.yaml#
88 "^fimc-is@[0-9a-f]+$":
90 $ref: samsung,exynos4212-fimc-is.yaml#
91 description: Imaging Subsystem (FIMC-IS).
93 "^fimc-lite@[0-9a-f]+$":
95 $ref: samsung,exynos4212-fimc-lite.yaml#
96 description: Camera host interface (FIMC-LITE).
99 - compatible
100 - '#address-cells'
101 - '#clock-cells'
102 - clocks
103 - clock-names
104 - clock-output-names
105 - ranges
106 - '#size-cells'
111 - |
112 #include <dt-bindings/clock/exynos4.h>
113 #include <dt-bindings/gpio/gpio.h>
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
118 #clock-cells = <1>;
119 #address-cells = <1>;
120 #size-cells = <1>;
125 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
126 clock-output-names = "cam_a_clkout", "cam_b_clkout";
128 assigned-clocks = <&clock CLK_MOUT_CAM0>,
130 assigned-clock-parents = <&clock CLK_XUSBXTI>,
133 pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
134 pinctrl-names = "default";
137 compatible = "samsung,exynos4212-fimc";
142 clock-names = "fimc", "sclk_fimc";
143 power-domains = <&pd_cam>;
144 samsung,sysreg = <&sys_reg>;
147 samsung,pix-limits = <4224 8192 1920 4224>;
148 samsung,mainscaler-ext;
149 samsung,isp-wb;
150 samsung,cam-if;
153 /* ... FIMC 1-3 */
156 compatible = "samsung,exynos4210-csis";
161 clock-names = "csis", "sclk_csis";
162 assigned-clocks = <&clock CLK_MOUT_CSIS0>,
164 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
165 assigned-clock-rates = <0>, <176000000>;
167 bus-width = <4>;
168 power-domains = <&pd_cam>;
170 phy-names = "csis";
171 #address-cells = <1>;
172 #size-cells = <0>;
174 vddcore-supply = <&ldo8_reg>;
175 vddio-supply = <&ldo10_reg>;
177 /* Camera C (3) MIPI CSI-2 (CSIS0) */
181 remote-endpoint = <&s5c73m3_ep>;
182 data-lanes = <1 2 3 4>;
183 samsung,csis-hs-settle = <12>;
190 fimc-lite@b90000 {
191 compatible = "samsung,exynos4212-fimc-lite";
194 power-domains = <&pd_isp>;
196 clock-names = "flite";
200 /* ... FIMC-LITE 1 */
202 fimc-is@800000 {
203 compatible = "samsung,exynos4212-fimc-is";
228 clock-names = "lite0", "lite1", "ppmuispx",
238 iommu-names = "isp", "drc", "fd", "mcuctl";
239 power-domains = <&pd_isp>;
240 samsung,pmu-syscon = <&pmu_system_controller>;
242 #address-cells = <1>;
243 #size-cells = <1>;
246 i2c-isp@940000 {
247 compatible = "samsung,exynos4212-i2c-isp";
250 clock-names = "i2c_isp";
251 pinctrl-0 = <&fimc_is_i2c1>;
252 pinctrl-names = "default";
253 #address-cells = <1>;
254 #size-cells = <0>;
256 image-sensor@10 {
259 svdda-supply = <&cam_io_reg>;
260 svddio-supply = <&ldo19_reg>;
261 afvdd-supply = <&ldo19_reg>;
262 clock-frequency = <24000000>;
265 clock-names = "extclk";
270 remote-endpoint = <&csis1_ep>;
271 data-lanes = <1>;