Lines Matching +full:exynos4 +full:- +full:sysreg
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-csis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 - samsung,s5pv210-csis
17 - samsung,exynos4210-csis
18 - samsung,exynos4212-csis
19 - samsung,exynos5250-csis
24 '#address-cells':
27 '#size-cells':
30 bus-width:
39 clock-names:
41 - const: csis
42 - const: sclk_csis
44 clock-frequency:
55 phy-names:
57 - const: csis
59 power-domains:
62 vddio-supply:
65 vddcore-supply:
70 $ref: /schemas/graph.yaml#/$defs/port-base
80 $ref: video-interfaces.yaml#
84 data-lanes:
88 samsung,csis-hs-settle:
90 description: Differential receiver (HS-RX) settle time.
92 samsung,csis-wclk:
95 CSI-2 wrapper clock selection. If this property is present external clock
99 - data-lanes
102 - reg
105 - compatible
106 - reg
107 - bus-width
108 - clocks
109 - clock-names
110 - interrupts
111 - vddio-supply
112 - vddcore-supply
115 - required:
116 - port@3
117 - required:
118 - port@4
121 - if:
123 - samsung,isp-wb
126 - samsung,sysreg
131 - |
132 #include <dt-bindings/clock/exynos4.h>
133 #include <dt-bindings/interrupt-controller/arm-gic.h>
136 compatible = "samsung,exynos4210-csis";
140 clock-names = "csis", "sclk_csis";
141 assigned-clocks = <&clock CLK_MOUT_CSIS1>,
143 assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>;
144 assigned-clock-rates = <0>, <176000000>;
148 bus-width = <2>;
149 power-domains = <&pd_cam>;
151 phy-names = "csis";
153 vddcore-supply = <&ldo8_reg>;
154 vddio-supply = <&ldo10_reg>;
156 #address-cells = <1>;
157 #size-cells = <0>;
159 /* Camera D (4) MIPI CSI-2 (CSIS1) */
164 remote-endpoint = <&is_s5k6a3_ep>;
165 data-lanes = <1>;
166 samsung,csis-hs-settle = <18>;
167 samsung,csis-wclk;