Lines Matching +full:one +full:- +full:channel
1 Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
2 ------------------------------------------------------------
4 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
7 +---------------------+ +---------------------+
8 | |-----SCK------->|CLK |
9 | Master |-----SS-------->|SYNC DRIFn (slave) |
10 | |-----SD0------->|D0 |
11 | |-----SD1------->|D1 |
12 +---------------------+ +---------------------+
14 As per datasheet, each DRIF channel (drifn) is made up of two internal
16 CLK & SYNC. Each internal channel has its own dedicated resources like
20 The device tree model represents each internal channel as a separate node.
23 the documentation, unless explicitly stated, the word channel implies an
24 internal channel.
27 as one (i.e.) they cannot operate alone as independent devices. Out of the
28 two, one of them needs to act as a primary device that accepts common
29 properties of both the internal channels. This channel is identified by a
30 property called "renesas,primary-bond".
33 - When both the internal channels that are bonded together are enabled,
34 the zeroth channel is selected as primary-bond. This channels accepts
36 - When only one of the bonded channels need to be enabled, the property
37 "renesas,bonding" or "renesas,primary-bond" will have no effect. That
38 enabled channel can act alone as any other independent device.
40 Required properties of an internal channel:
41 -------------------------------------------
42 - compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
43 "renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
44 "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
47 SoC-specific version corresponding to the platform first
50 - reg: offset and length of that channel.
51 - interrupts: associated with that channel.
52 - clocks: phandle and clock specifier of that channel.
53 - clock-names: clock input name string: "fck".
54 - dmas: phandles to the DMA channels.
55 - dma-names: names of the DMA channel: "rx".
56 - renesas,bonding: phandle to the other channel.
58 Optional properties of an internal channel:
59 -------------------------------------------
60 - power-domains: phandle to the respective power domain.
62 Required properties of an internal channel when:
63 - It is the only enabled channel of the bond (or)
64 - If it acts as primary among enabled bonds
65 --------------------------------------------------------
66 - pinctrl-0: pin control group to be used for this channel.
67 - pinctrl-names: must be "default".
68 - renesas,primary-bond: empty property indicating the channel acts as primary
70 - port: child port node corresponding to the data input, in accordance with
72 Documentation/devicetree/bindings/media/video-interfaces.txt. The port
73 node must contain at least one endpoint.
76 ---------------------------
77 - sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
82 --------
85 -----------------------------------
90 +---------------------+ +---------------------+
91 | |-----SCK------->|CLK |
92 | Master |-----SS-------->|SYNC DRIFn (slave) |
93 | |-----SD0------->|D0 |
94 | |-----SD1------->|D1 |
95 +---------------------+ +---------------------+
98 compatible = "renesas,r8a7795-drif",
99 "renesas,rcar-gen3-drif";
103 clock-names = "fck";
105 dma-names = "rx", "rx";
106 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
108 renesas,primary-bond;
109 pinctrl-0 = <&drif0_pins>;
110 pinctrl-names = "default";
113 remote-endpoint = <&tuner_ep>;
119 compatible = "renesas,r8a7795-drif",
120 "renesas,rcar-gen3-drif";
124 clock-names = "fck";
126 dma-names = "rx", "rx";
127 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
132 (2) Internal channel 1 alone is enabled:
133 ----------------------------------------
135 When interfacing with a third party tuner device with one data pin as shown
138 +---------------------+ +---------------------+
139 | |-----SCK------->|CLK |
140 | Master |-----SS-------->|SYNC DRIFn (slave) |
142 | |-----SD-------->|D1 |
143 +---------------------+ +---------------------+
146 compatible = "renesas,r8a7795-drif",
147 "renesas,rcar-gen3-drif";
151 clock-names = "fck";
153 dma-names = "rx", "rx";
154 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
159 compatible = "renesas,r8a7795-drif",
160 "renesas,rcar-gen3-drif";
164 clock-names = "fck";
166 dma-names = "rx", "rx";
167 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
169 pinctrl-0 = <&drif0_pins>;
170 pinctrl-names = "default";
173 remote-endpoint = <&tuner_ep>;
174 sync-active = <0>;