Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
26 - fsl,imx7-mipi-csi2
27 - fsl,imx8mm-mipi-csi2
38 - description: The peripheral clock (a.k.a. APB clock)
39 - description: The external clock (optionally used as the pixel clock)
40 - description: The MIPI D-PHY clock
41 - description: The AXI clock
43 clock-names:
46 - const: pclk
47 - const: wrap
48 - const: phy
49 - const: axi
51 power-domains:
54 phy-supply:
55 description: The MIPI D-PHY digital power supply
59 - description: MIPI D-PHY slave reset
61 clock-frequency:
66 $ref: /schemas/graph.yaml#/properties/ports
70 $ref: /schemas/graph.yaml#/$defs/port-base
73 Input port node, single endpoint describing the CSI-2 transmitter.
77 $ref: video-interfaces.yaml#
81 data-lanes:
83 Note that 'fsl,imx7-mipi-csi2' only supports up to 2 data lines.
86 - const: 1
87 - const: 2
88 - const: 3
89 - const: 4
92 - data-lanes
95 $ref: /schemas/graph.yaml#/properties/port
100 - compatible
101 - reg
102 - interrupts
103 - clocks
104 - clock-names
105 - power-domains
106 - ports
111 - if:
115 const: fsl,imx7-mipi-csi2
118 - phy-supply
119 - resets
124 clock-names:
126 phy-supply: false
130 - |
131 #include <dt-bindings/clock/imx7d-clock.h>
132 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 #include <dt-bindings/interrupt-controller/irq.h>
134 #include <dt-bindings/reset/imx7-reset.h>
136 mipi-csi@30750000 {
137 compatible = "fsl,imx7-mipi-csi2";
144 clock-names = "pclk", "wrap", "phy";
145 clock-frequency = <166000000>;
147 power-domains = <&pgc_mipi_phy>;
148 phy-supply = <®_1p0d>;
152 #address-cells = <1>;
153 #size-cells = <0>;
159 remote-endpoint = <&ov2680_to_mipi>;
160 data-lanes = <1>;
168 remote-endpoint = <&csi_mux_from_mipi_vc0>;
174 - |
175 #include <dt-bindings/clock/imx8mm-clock.h>
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
177 #include <dt-bindings/interrupt-controller/irq.h>
179 mipi-csi@32e30000 {
180 compatible = "fsl,imx8mm-mipi-csi2";
183 clock-frequency = <333000000>;
184 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
185 <&clk IMX8MM_CLK_CSI1_ROOT>,
186 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
187 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
188 clock-names = "pclk", "wrap", "phy", "axi";
189 power-domains = <&mipi_pd>;
192 #address-cells = <1>;
193 #size-cells = <0>;
199 remote-endpoint = <&imx477_out>;
200 data-lanes = <1 2 3 4>;
208 remote-endpoint = <&csi_in>;