Lines Matching +full:mt8183 +full:- +full:scp

7 - compatible : must be one of the following string:
8   "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9   "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10   "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11   "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12   "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13   "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
14   "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
15 - reg : Physical base address of the video codec registers and length of
17 - interrupts : interrupt number to the cpu.
18 - mediatek,larb : must contain the local arbiters in the current Socs.
19 - clocks : list of clock specifiers, corresponding to entries in
20   the clock-names property.
21 - clock-names: avc encoder must contain "venc_sel", vp8 encoder must
25 - iommus : should point to the respective IOMMU block with master port as
28 - dma-ranges : describes the dma address range space that the codec hw access.
30 - mediatek,vpu : the node of the video processor unit, if using VPU.
31 - mediatek,scp : the node of the SCP unit, if using SCP.
37     compatible = "mediatek,mt8173-vcodec-dec";
61     power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
70     clock-names = "vcodecpll",
78     assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
83     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
86     assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
90     compatible = "mediatek,mt8173-vcodec-enc";
107     clock-names = "venc_sel";
108     assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
109     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
113     compatible = "mediatek,mt8173-vcodec-enc-vp8";
128     clock-names = "venc_lt_sel";
129     assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
130     assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;