Lines Matching +full:0 +full:x19002000
38 reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
39 <0 0x16020000 0 0x1000>, /*VDEC_MISC*/
40 <0 0x16021000 0 0x800>, /*VDEC_LD*/
41 <0 0x16021800 0 0x800>, /*VDEC_TOP*/
42 <0 0x16022000 0 0x1000>, /*VDEC_CM*/
43 <0 0x16023000 0 0x1000>, /*VDEC_AD*/
44 <0 0x16024000 0 0x1000>, /*VDEC_AV*/
45 <0 0x16025000 0 0x1000>, /*VDEC_PP*/
46 <0 0x16026800 0 0x800>, /*VP8_VD*/
47 <0 0x16027000 0 0x800>, /*VP6_VD*/
48 <0 0x16027800 0 0x800>, /*VP8_VL*/
49 <0 0x16028400 0 0x400>; /*VP9_VD*/
86 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
91 reg = <0 0x18002000 0 0x1000>;
114 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */