Lines Matching full:hardware

7 title: MediaTek Video Decode Accelerator With Multi Hardware
13   MediaTek Video Decode Accelerator is the video decoding hardware present in
17   The decoder hardware block diagram is shown below:
34   The child nodes represent the individual hardware blocks within the decoding
37   hardware, such as clocks, power domains, interrupts and IOMMUs.
42   handles V4L2 API calls on behalf of the underlying hardware.
46      Its workers take input bitstream and LAT buffer, enable the hardware for
47      decoding tasks, write the result to LAT buffer, and disable the hardware
50      Its workers take LAT buffer and output buffer, enable the hardware for
51      decoding tasks, write the result to output buffer, and disable the hardware
54   These hardware decode each frame cyclically.
56   The hardware might be associated with different SMI-common devices.
57   To prevent IOMMU faults during DRAM access in such cases, each hardware with
61   LAT-SoC refers to another hardware block that connected to additional LARB
90       List of the hardware port in respective IOMMU block for current Socs.
130           List of the hardware port in respective IOMMU block for current Socs.