Lines Matching +full:mt8183 +full:- +full:mdp3 +full:- +full:wrot

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Matthias Brugger <matthias.bgg@gmail.com>
11   - Moudy Ho <moudy.ho@mediatek.com>
14   One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
19       - enum:
20           - mediatek,mt8183-mdp3-wrot
21       - items:
22           - enum:
23               - mediatek,mt8195-mdp3-wrot
24           - const: mediatek,mt8183-mdp3-wrot
29   mediatek,gce-client-reg:
30     $ref: /schemas/types.yaml#/definitions/phandle-array
33         - description: phandle of GCE
34         - description: GCE subsys id
35         - description: register offset
36         - description: register size
39       a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
41   mediatek,gce-events:
45       include/dt-bindings/gce/<chip>-gce.h of each chips.
46     $ref: /schemas/types.yaml#/definitions/uint32-array
48   power-domains:
57   '#dma-cells':
61   - compatible
62   - reg
63   - mediatek,gce-client-reg
64   - mediatek,gce-events
65   - power-domains
66   - clocks
67   - iommus
68   - '#dma-cells'
73   - |
74     #include <dt-bindings/clock/mt8183-clk.h>
75     #include <dt-bindings/gce/mt8183-gce.h>
76     #include <dt-bindings/power/mt8183-power.h>
77     #include <dt-bindings/memory/mt8183-larb-port.h>
79     dma-controller@14005000 {
80         compatible = "mediatek,mt8183-mdp3-wrot";
82         mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
83         mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
85         power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
88         #dma-cells = <1>;