Lines Matching +full:st +full:- +full:mipid02
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/i2c/st,st-mipid02.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
10 - Benjamin Mugnier <benjamin.mugnier@foss.st.com>
11 - Sylvain Petinot <sylvain.petinot@foss.st.com>
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
15 active at a time. Active port input stream will be de-serialized
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
22 RGB444, YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
26 const: st,st-mipid02
34 clock-names:
37 VDDE-supply:
41 VDDIN-supply:
45 reset-gpios:
48 This is an active low signal to the mipid02.
54 $ref: /schemas/graph.yaml#/$defs/port-base
56 description: CSI-2 first input port
59 $ref: /schemas/media/video-interfaces.yaml#
63 data-lanes:
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
77 - data-lanes
80 $ref: /schemas/graph.yaml#/$defs/port-base
82 description: CSI-2 second input port
85 $ref: /schemas/media/video-interfaces.yaml#
89 data-lanes:
91 Single-lane operation shall be <1> or <2> .
94 lane-polarities:
100 - data-lanes
103 $ref: /schemas/graph.yaml#/$defs/port-base
108 $ref: /schemas/media/video-interfaces.yaml#
112 bus-width:
116 - bus-width
119 - required:
120 - port@0
121 - required:
122 - port@1
125 - port@2
130 - compatible
131 - reg
132 - clocks
133 - clock-names
134 - VDDE-supply
135 - VDDIN-supply
136 - ports
139 - |
141 #address-cells = <1>;
142 #size-cells = <0>;
143 mipid02: csi2rx@14 {
144 compatible = "st,st-mipid02";
147 clock-names = "xclk";
148 VDDE-supply = <&vdd>;
149 VDDIN-supply = <&vdd>;
151 #address-cells = <1>;
152 #size-cells = <0>;
157 data-lanes = <1 2>;
158 remote-endpoint = <&mipi_csi2_in>;
165 bus-width = <8>;
166 hsync-active = <0>;
167 vsync-active = <0>;
168 remote-endpoint = <¶llel_out>;