Lines Matching +full:st +full:- +full:mipid02
1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
21 - reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
22 This is an active low signal to the mipid02.
25 - ports: A ports node with one port child node per device input and output
27 Documentation/devicetree/bindings/media/video-interfaces.txt. The
31 -----------------------------
32 0 CSI-2 first input port
33 1 CSI-2 second input port
36 Endpoint node required property for CSI-2 connection is:
37 - data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
39 Endpoint node optional property for CSI-2 connection is:
40 - lane-polarities: any lane can be inverted or not.
43 - bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
45 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
47 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
52 mipid02: csi2rx@14 {
53 compatible = "st,st-mipid02";
57 clock-names = "xclk";
58 VDDE-supply = <&vdd>;
59 VDDIN-supply = <&vdd>;
61 #address-cells = <1>;
62 #size-cells = <0>;
67 data-lanes = <1 2>;
68 remote-endpoint = <&mipi_csi2_in>;
75 bus-width = <8>;
76 hsync-active = <0>;
77 vsync-active = <0>;
78 remote-endpoint = <¶llel_out>;