Lines Matching refs:master

2 master(s).
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
48   This may also apply to multiple master IOMMU devices that do not allow the
50   be multi-master yet only expose a single master in a given configuration.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
53   in order to enable translation for a given master. In such cases the single
54   address cell corresponds to the master device's ID. In some cases more than
55   one cell can be required to represent a single master ID.
57   be configured. The first cell of the address in this may contain the master
67 IOMMU master node:
71 have multiple master interfaces (to one or more IOMMU devices).
76   master interfaces of the device. One entry in the list describes one master
95 - dma-can-stall: When present, the master can wait for a transaction to
102   having to either put back-pressure on the master, or abort new faulting
129 Single-master IOMMU:
136 	master {
140 Multiple-master IOMMU with fixed associations:
143 	/* multiple-master IOMMU */
157 	master@1 {
163 	master@2 {
168 Multiple-master IOMMU:
172 		/* the specifier represents the ID of the master */
176 	master@1 {
177 		/* device has master ID 42 in the IOMMU */
181 	master@2 {
182 		/* device has master IDs 23 and 24 in the IOMMU */
186 Multiple-master IOMMU with configurable DMA window:
192 			 * One cell for the master ID and one cell for the
197 			 * master (i.e. the I/O virtual address space).
202 		master {
203 			/* master ID 42, 4 GiB DMA window starting at 0 */