Lines Matching +full:single +full:- +full:master
2 master(s).
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
48 This may also apply to multiple master IOMMU devices that do not allow the
50 be multi-master yet only expose a single master in a given configuration.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
53 in order to enable translation for a given master. In such cases the single
54 address cell corresponds to the master device's ID. In some cases more than
55 one cell can be required to represent a single master ID.
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
57 be configured. The first cell of the address in this may contain the master
62 Note that these are merely examples and real-world use-cases may use different
67 IOMMU master node:
71 have multiple master interfaces (to one or more IOMMU devices).
74 --------------------
75 - iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
76 master interfaces of the device. One entry in the list describes one master
80 be used for address translation. If a "dma-ranges" property exists in the
82 referenced IOMMU is disabled, in which case the "dma-ranges" property of the
90 --------------------
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
95 - dma-can-stall: When present, the master can wait for a transaction to
102 having to either put back-pressure on the master, or abort new faulting
105 Firmware has to opt-in stalling, because most buses and masters don't
118 a "dma-ranges" property in a bus device node (such as PCI host bridges). This
121 requirements of that use-case haven't been fully determined yet. Implementing
129 Single-master IOMMU:
130 --------------------
133 #iommu-cells = <0>;
136 master {
140 Multiple-master IOMMU with fixed associations:
141 ----------------------------------------------
143 /* multiple-master IOMMU */
153 #iommu-cells = <0>;
157 master@1 {
163 master@2 {
168 Multiple-master IOMMU:
169 ----------------------
172 /* the specifier represents the ID of the master */
173 #iommu-cells = <1>;
176 master@1 {
177 /* device has master ID 42 in the IOMMU */
181 master@2 {
182 /* device has master IDs 23 and 24 in the IOMMU */
186 Multiple-master IOMMU with configurable DMA window:
187 ---------------------------------------------------
192 * One cell for the master ID and one cell for the
197 * master (i.e. the I/O virtual address space).
199 #iommu-cells = <4>;
202 master {
203 /* master ID 42, 4 GiB DMA window starting at 0 */