Lines Matching +full:dma +full:- +full:window

13   Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
18 * Provide system protection against "rogue" DMA by forcing all accesses to go
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
44 the specific IOMMU. Below are a few examples of typical use-cases:
46 - #iommu-cells = <0>: Single master IOMMU devices are not configurable and
50   be multi-master yet only expose a single master in a given configuration.
52 - #iommu-cells = <1>: Multiple master IOMMU devices may need to be configured
56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to
59   the DMA window for the given device. The length of the DMA window is given
62 Note that these are merely examples and real-world use-cases may use different
74 --------------------
75 - iommus: A list of phandle and IOMMU specifier pairs that describe the IOMMU
80 be used for address translation. If a "dma-ranges" property exists in the
82 referenced IOMMU is disabled, in which case the "dma-ranges" property of the
90 --------------------
91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by
92   tagging DMA transactions with an address space identifier. By default,
95 - dma-can-stall: When present, the master can wait for a transaction to
102   having to either put back-pressure on the master, or abort new faulting
105   Firmware has to opt-in stalling, because most buses and masters don't
118 a "dma-ranges" property in a bus device node (such as PCI host bridges). This
121 requirements of that use-case haven't been fully determined yet. Implementing
129 Single-master IOMMU:
130 --------------------
133 		#iommu-cells = <0>;
140 Multiple-master IOMMU with fixed associations:
141 ----------------------------------------------
143 	/* multiple-master IOMMU */
153 		#iommu-cells = <0>;
168 Multiple-master IOMMU:
169 ----------------------
173 		#iommu-cells = <1>;
186 Multiple-master IOMMU with configurable DMA window:
187 ---------------------------------------------------
193 			 * address of the DMA window. The length of the DMA
194 			 * window is encoded in two cells.
196 			 * The DMA window is the range addressable by the
199 			#iommu-cells = <4>;
203 			/* master ID 42, 4 GiB DMA window starting at 0 */