Lines Matching +full:stream +full:- +full:match +full:- +full:mask
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
37 - enum:
38 - qcom,qcm2290-smmu-500
39 - qcom,qcs8300-smmu-500
40 - qcom,qdu1000-smmu-500
41 - qcom,sa8255p-smmu-500
42 - qcom,sa8775p-smmu-500
43 - qcom,sc7180-smmu-500
44 - qcom,sc7280-smmu-500
45 - qcom,sc8180x-smmu-500
46 - qcom,sc8280xp-smmu-500
47 - qcom,sdm670-smmu-500
48 - qcom,sdm845-smmu-500
49 - qcom,sdx55-smmu-500
50 - qcom,sdx65-smmu-500
51 - qcom,sdx75-smmu-500
52 - qcom,sm6115-smmu-500
53 - qcom,sm6125-smmu-500
54 - qcom,sm6350-smmu-500
55 - qcom,sm6375-smmu-500
56 - qcom,sm8150-smmu-500
57 - qcom,sm8250-smmu-500
58 - qcom,sm8350-smmu-500
59 - qcom,sm8450-smmu-500
60 - qcom,sm8550-smmu-500
61 - qcom,sm8650-smmu-500
62 - qcom,x1e80100-smmu-500
63 - const: qcom,smmu-500
64 - const: arm,mmu-500
66 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
70 - enum:
71 - qcom,qcm2290-smmu-500
72 - qcom,sc7180-smmu-500
73 - qcom,sc7280-smmu-500
74 - qcom,sc8180x-smmu-500
75 - qcom,sc8280xp-smmu-500
76 - qcom,sdm845-smmu-500
77 - qcom,sm6115-smmu-500
78 - qcom,sm6350-smmu-500
79 - qcom,sm6375-smmu-500
80 - qcom,sm8150-smmu-500
81 - qcom,sm8250-smmu-500
82 - qcom,sm8350-smmu-500
83 - qcom,sm8450-smmu-500
84 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
87 - enum:
88 - qcom,qcm2290-smmu-500
89 - qcom,sa8255p-smmu-500
90 - qcom,sa8775p-smmu-500
91 - qcom,sc7280-smmu-500
92 - qcom,sc8180x-smmu-500
93 - qcom,sc8280xp-smmu-500
94 - qcom,sm6115-smmu-500
95 - qcom,sm6125-smmu-500
96 - qcom,sm8150-smmu-500
97 - qcom,sm8250-smmu-500
98 - qcom,sm8350-smmu-500
99 - qcom,sm8450-smmu-500
100 - qcom,sm8550-smmu-500
101 - qcom,sm8650-smmu-500
102 - qcom,x1e80100-smmu-500
103 - const: qcom,adreno-smmu
104 - const: qcom,smmu-500
105 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
110 - enum:
111 - qcom,sc7280-smmu-500
112 - qcom,sm8150-smmu-500
113 - qcom,sm8250-smmu-500
114 - const: qcom,adreno-smmu
115 - const: arm,mmu-500
116 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
118 - enum:
119 - qcom,msm8996-smmu-v2
120 - qcom,sc7180-smmu-v2
121 - qcom,sdm630-smmu-v2
122 - qcom,sdm845-smmu-v2
123 - qcom,sm6350-smmu-v2
124 - qcom,sm7150-smmu-v2
125 - const: qcom,adreno-smmu
126 - const: qcom,smmu-v2
127 - description: Qcom Adreno GPUs on Google Cheza platform
129 - const: qcom,sdm845-smmu-v2
130 - const: qcom,smmu-v2
131 - description: Marvell SoCs implementing "arm,mmu-500"
133 - const: marvell,ap806-smmu-500
134 - const: arm,mmu-500
135 - description: NVIDIA SoCs that require memory controller interaction
136 and may program multiple ARM MMU-500s identically with the memory
140 - enum:
141 - nvidia,tegra186-smmu
142 - nvidia,tegra194-smmu
143 - nvidia,tegra234-smmu
144 - const: nvidia,smmu-500
145 - items:
146 - const: arm,mmu-500
147 - const: arm,smmu-v2
148 - items:
149 - enum:
150 - arm,mmu-400
151 - arm,mmu-401
152 - const: arm,smmu-v1
153 - enum:
154 - arm,smmu-v1
155 - arm,smmu-v2
156 - arm,mmu-400
157 - arm,mmu-401
158 - arm,mmu-500
159 - cavium,smmu-v2
165 '#global-interrupts':
169 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
171 '#iommu-cells':
175 value of 1, each IOMMU specifier represents a distinct stream ID emitted
178 SMMUs with stream matching support and complex masters may use a value of
179 2, where the second cell of the IOMMU specifier represents an SMR mask to
187 Interrupt list, with the first #global-interrupts entries corresponding to
195 dma-coherent:
203 calxeda,smmu-secure-config-access:
207 access to SMMU configuration registers. In this case non-secure aliases of
210 stream-match-mask:
213 For SMMUs supporting stream matching and using #iommu-cells = <1>,
214 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
215 be programmed into the SMRn.MASK field of every stream match register
217 Stream ID (e.g. for certain MMU-500 configurations given globally unique
218 input IDs). This property is not valid for SMMUs using stream indexing, or
219 using stream matching with #iommu-cells = <2>, and may be ignored if
222 clock-names:
230 power-domains:
234 nvidia,memory-controller:
238 client IDs to ARM SMMU stream IDs.
246 - compatible
247 - reg
248 - '#global-interrupts'
249 - '#iommu-cells'
250 - interrupts
255 - if:
260 - nvidia,tegra186-smmu
261 - nvidia,tegra194-smmu
262 - nvidia,tegra234-smmu
270 # memory client to stream ID mapping can be done synchronously with the
273 - nvidia,memory-controller
279 - if:
284 - qcom,msm8998-smmu-v2
285 - qcom,sdm630-smmu-v2
288 - properties:
289 clock-names:
291 - const: bus
294 - description: bus clock required for downstream bus access and for
296 - properties:
297 clock-names:
299 - const: iface
300 - const: mem
301 - const: mem_iface
304 - description: interface clock required to access smmu's registers
306 - description: bus clock required for memory access
307 - description: bus clock required for GPU memory access
308 - properties:
309 clock-names:
311 - const: iface-mm
312 - const: iface-smmu
313 - const: bus-smmu
316 - description: interface clock required to access mnoc's registers
318 - description: interface clock required to access smmu's registers
320 - description: bus clock required for the smmu ptw
322 - if:
327 - qcom,sm6375-smmu-v2
330 - properties:
331 clock-names:
333 - const: bus
336 - description: bus clock required for downstream bus access and for
338 - properties:
339 clock-names:
341 - const: iface
342 - const: mem
343 - const: mem_iface
346 - description: interface clock required to access smmu's registers
348 - description: bus clock required for memory access
349 - description: bus clock required for GPU memory access
350 - properties:
351 clock-names:
353 - const: iface-mm
354 - const: iface-smmu
355 - const: bus-mm
356 - const: bus-smmu
359 - description: interface clock required to access mnoc's registers
361 - description: interface clock required to access smmu's registers
363 - description: bus clock required for downstream bus access
364 - description: bus clock required for the smmu ptw
366 - if:
371 - qcom,msm8996-smmu-v2
372 - qcom,sc7180-smmu-v2
373 - qcom,sdm845-smmu-v2
376 clock-names:
378 - const: bus
379 - const: iface
383 - description: bus clock required for downstream bus access and for
385 - description: interface clock required to access smmu's registers
388 - if:
393 - qcom,sa8775p-smmu-500
394 - qcom,sc7280-smmu-500
395 - qcom,sc8280xp-smmu-500
398 clock-names:
400 - const: gcc_gpu_memnoc_gfx_clk
401 - const: gcc_gpu_snoc_dvm_gfx_clk
402 - const: gpu_cc_ahb_clk
403 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
404 - const: gpu_cc_cx_gmu_clk
405 - const: gpu_cc_hub_cx_int_clk
406 - const: gpu_cc_hub_aon_clk
410 - description: GPU memnoc_gfx clock
411 - description: GPU snoc_dvm_gfx clock
412 - description: GPU ahb clock
413 - description: GPU hlos1_vote_GPU smmu clock
414 - description: GPU cx_gmu clock
415 - description: GPU hub_cx_int clock
416 - description: GPU hub_aon clock
418 - if:
423 - qcom,sc8180x-smmu-500
424 - qcom,sm6350-smmu-v2
425 - qcom,sm7150-smmu-v2
426 - qcom,sm8150-smmu-500
427 - qcom,sm8250-smmu-500
430 clock-names:
432 - const: ahb
433 - const: bus
434 - const: iface
438 - description: bus clock required for AHB bus access
439 - description: bus clock required for downstream bus access and for
441 - description: interface clock required to access smmu's registers
444 - if:
448 - enum:
449 - qcom,sm8350-smmu-500
450 - const: qcom,adreno-smmu
451 - const: qcom,smmu-500
452 - const: arm,mmu-500
455 clock-names:
457 - const: bus
458 - const: iface
459 - const: ahb
460 - const: hlos1_vote_gpu_smmu
461 - const: cx_gmu
462 - const: hub_cx_int
463 - const: hub_aon
468 - if:
472 - enum:
473 - qcom,qcm2290-smmu-500
474 - qcom,sm6115-smmu-500
475 - qcom,sm6125-smmu-500
476 - const: qcom,adreno-smmu
477 - const: qcom,smmu-500
478 - const: arm,mmu-500
481 clock-names:
483 - const: mem
484 - const: hlos
485 - const: iface
489 - description: GPU memory bus clock
490 - description: Voter clock required for HLOS SMMU access
491 - description: Interface clock required for register access
493 - if:
497 - const: qcom,sm8450-smmu-500
498 - const: qcom,adreno-smmu
499 - const: qcom,smmu-500
500 - const: arm,mmu-500
504 clock-names:
506 - const: gmu
507 - const: hub
508 - const: hlos
509 - const: bus
510 - const: iface
511 - const: ahb
515 - description: GMU clock
516 - description: GPU HUB clock
517 - description: HLOS vote clock
518 - description: GPU memory bus clock
519 - description: GPU SNoC bus clock
520 - description: GPU AHB clock
522 - if:
526 - enum:
527 - qcom,sm8550-smmu-500
528 - qcom,sm8650-smmu-500
529 - qcom,x1e80100-smmu-500
530 - const: qcom,adreno-smmu
531 - const: qcom,smmu-500
532 - const: arm,mmu-500
535 clock-names:
537 - const: hlos
538 - const: bus
539 - const: iface
540 - const: ahb
544 - description: HLOS vote clock
545 - description: GPU memory bus clock
546 - description: GPU SNoC bus clock
547 - description: GPU AHB clock
550 - if:
555 - cavium,smmu-v2
556 - marvell,ap806-smmu-500
557 - nvidia,smmu-500
558 - qcom,qcs8300-smmu-500
559 - qcom,qdu1000-smmu-500
560 - qcom,sa8255p-smmu-500
561 - qcom,sc7180-smmu-500
562 - qcom,sdm670-smmu-500
563 - qcom,sdm845-smmu-500
564 - qcom,sdx55-smmu-500
565 - qcom,sdx65-smmu-500
566 - qcom,sm6350-smmu-500
567 - qcom,sm6375-smmu-500
570 clock-names: false
573 - if:
577 const: qcom,sm6375-smmu-500
580 power-domains:
582 - description: SNoC MMU TBU RT GDSC
583 - description: SNoC MMU TBU NRT GDSC
584 - description: SNoC TURING MMU TBU0 GDSC
587 - power-domains
590 power-domains:
594 - |+
595 /* SMMU with stream matching or stream indexing */
597 compatible = "arm,smmu-v1";
599 #global-interrupts = <2>;
606 #iommu-cells = <1>;
609 /* device with two stream IDs, 0 and 7 */
616 /* SMMU with stream matching */
618 compatible = "arm,smmu-v1";
620 #global-interrupts = <2>;
627 #iommu-cells = <2>;
630 /* device with stream IDs 0 and 7 */
636 /* device with stream IDs 1, 17, 33 and 49 */
642 /* ARM MMU-500 with 10-bit stream ID input configuration */
644 compatible = "arm,mmu-500", "arm,smmu-v2";
646 #global-interrupts = <2>;
653 #iommu-cells = <1>;
654 /* always ignore appended 5-bit TBU number */
655 stream-match-mask = <0x7c00>;
659 /* bus whose child devices emit one unique 10-bit stream
661 iommu-map = <0 &smmu3 0 0x400>;
666 - |+
667 /* Qcom's arm,smmu-v2 implementation */
668 #include <dt-bindings/interrupt-controller/arm-gic.h>
669 #include <dt-bindings/interrupt-controller/irq.h>
671 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
674 #global-interrupts = <1>;
678 #iommu-cells = <1>;
679 power-domains = <&mmcc 0>;
683 clock-names = "bus", "iface";