Lines Matching +full:mmu +full:- +full:500
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
31 - qcom,sdm630-smmu-v2
32 - qcom,sm6375-smmu-v2
33 - const: qcom,smmu-v2
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
37 - enum:
38 - qcom,qcm2290-smmu-500
39 - qcom,qdu1000-smmu-500
40 - qcom,sa8775p-smmu-500
41 - qcom,sc7180-smmu-500
42 - qcom,sc7280-smmu-500
43 - qcom,sc8180x-smmu-500
44 - qcom,sc8280xp-smmu-500
45 - qcom,sdm670-smmu-500
46 - qcom,sdm845-smmu-500
47 - qcom,sdx55-smmu-500
48 - qcom,sdx65-smmu-500
49 - qcom,sdx75-smmu-500
50 - qcom,sm6115-smmu-500
51 - qcom,sm6125-smmu-500
52 - qcom,sm6350-smmu-500
53 - qcom,sm6375-smmu-500
54 - qcom,sm8150-smmu-500
55 - qcom,sm8250-smmu-500
56 - qcom,sm8350-smmu-500
57 - qcom,sm8450-smmu-500
58 - qcom,sm8550-smmu-500
59 - qcom,sm8650-smmu-500
60 - qcom,x1e80100-smmu-500
61 - const: qcom,smmu-500
62 - const: arm,mmu-500
64 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
68 - enum:
69 - qcom,qcm2290-smmu-500
70 - qcom,sc7180-smmu-500
71 - qcom,sc7280-smmu-500
72 - qcom,sc8180x-smmu-500
73 - qcom,sc8280xp-smmu-500
74 - qcom,sdm845-smmu-500
75 - qcom,sm6115-smmu-500
76 - qcom,sm6350-smmu-500
77 - qcom,sm6375-smmu-500
78 - qcom,sm8150-smmu-500
79 - qcom,sm8250-smmu-500
80 - qcom,sm8350-smmu-500
81 - qcom,sm8450-smmu-500
82 - const: arm,mmu-500
83 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
85 - enum:
86 - qcom,sa8775p-smmu-500
87 - qcom,sc7280-smmu-500
88 - qcom,sc8280xp-smmu-500
89 - qcom,sm6115-smmu-500
90 - qcom,sm6125-smmu-500
91 - qcom,sm8150-smmu-500
92 - qcom,sm8250-smmu-500
93 - qcom,sm8350-smmu-500
94 - qcom,sm8450-smmu-500
95 - qcom,sm8550-smmu-500
96 - const: qcom,adreno-smmu
97 - const: qcom,smmu-500
98 - const: arm,mmu-500
99 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
103 - enum:
104 - qcom,sc7280-smmu-500
105 - qcom,sm8150-smmu-500
106 - qcom,sm8250-smmu-500
107 - const: qcom,adreno-smmu
108 - const: arm,mmu-500
109 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
111 - enum:
112 - qcom,msm8996-smmu-v2
113 - qcom,sc7180-smmu-v2
114 - qcom,sdm630-smmu-v2
115 - qcom,sdm845-smmu-v2
116 - qcom,sm6350-smmu-v2
117 - qcom,sm7150-smmu-v2
118 - const: qcom,adreno-smmu
119 - const: qcom,smmu-v2
120 - description: Qcom Adreno GPUs on Google Cheza platform
122 - const: qcom,sdm845-smmu-v2
123 - const: qcom,smmu-v2
124 - description: Marvell SoCs implementing "arm,mmu-500"
126 - const: marvell,ap806-smmu-500
127 - const: arm,mmu-500
128 - description: NVIDIA SoCs that require memory controller interaction
129 and may program multiple ARM MMU-500s identically with the memory
133 - enum:
134 - nvidia,tegra186-smmu
135 - nvidia,tegra194-smmu
136 - nvidia,tegra234-smmu
137 - const: nvidia,smmu-500
138 - items:
139 - const: arm,mmu-500
140 - const: arm,smmu-v2
141 - items:
142 - enum:
143 - arm,mmu-400
144 - arm,mmu-401
145 - const: arm,smmu-v1
146 - enum:
147 - arm,smmu-v1
148 - arm,smmu-v2
149 - arm,mmu-400
150 - arm,mmu-401
151 - arm,mmu-500
152 - cavium,smmu-v2
158 '#global-interrupts':
162 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
164 '#iommu-cells':
180 Interrupt list, with the first #global-interrupts entries corresponding to
188 dma-coherent:
196 calxeda,smmu-secure-config-access:
200 access to SMMU configuration registers. In this case non-secure aliases of
203 stream-match-mask:
206 For SMMUs supporting stream matching and using #iommu-cells = <1>,
210 Stream ID (e.g. for certain MMU-500 configurations given globally unique
212 using stream matching with #iommu-cells = <2>, and may be ignored if
215 clock-names:
223 power-domains:
227 nvidia,memory-controller:
239 - compatible
240 - reg
241 - '#global-interrupts'
242 - '#iommu-cells'
243 - interrupts
248 - if:
253 - nvidia,tegra186-smmu
254 - nvidia,tegra194-smmu
255 - nvidia,tegra234-smmu
266 - nvidia,memory-controller
272 - if:
277 - qcom,msm8998-smmu-v2
278 - qcom,sdm630-smmu-v2
281 - properties:
282 clock-names:
284 - const: bus
287 - description: bus clock required for downstream bus access and for
289 - properties:
290 clock-names:
292 - const: iface
293 - const: mem
294 - const: mem_iface
297 - description: interface clock required to access smmu's registers
299 - description: bus clock required for memory access
300 - description: bus clock required for GPU memory access
301 - properties:
302 clock-names:
304 - const: iface-mm
305 - const: iface-smmu
306 - const: bus-smmu
309 - description: interface clock required to access mnoc's registers
311 - description: interface clock required to access smmu's registers
313 - description: bus clock required for the smmu ptw
315 - if:
320 - qcom,sm6375-smmu-v2
323 - properties:
324 clock-names:
326 - const: bus
329 - description: bus clock required for downstream bus access and for
331 - properties:
332 clock-names:
334 - const: iface
335 - const: mem
336 - const: mem_iface
339 - description: interface clock required to access smmu's registers
341 - description: bus clock required for memory access
342 - description: bus clock required for GPU memory access
343 - properties:
344 clock-names:
346 - const: iface-mm
347 - const: iface-smmu
348 - const: bus-mm
349 - const: bus-smmu
352 - description: interface clock required to access mnoc's registers
354 - description: interface clock required to access smmu's registers
356 - description: bus clock required for downstream bus access
357 - description: bus clock required for the smmu ptw
359 - if:
364 - qcom,msm8996-smmu-v2
365 - qcom,sc7180-smmu-v2
366 - qcom,sdm845-smmu-v2
369 clock-names:
371 - const: bus
372 - const: iface
376 - description: bus clock required for downstream bus access and for
378 - description: interface clock required to access smmu's registers
381 - if:
386 - qcom,sa8775p-smmu-500
387 - qcom,sc7280-smmu-500
388 - qcom,sc8280xp-smmu-500
391 clock-names:
393 - const: gcc_gpu_memnoc_gfx_clk
394 - const: gcc_gpu_snoc_dvm_gfx_clk
395 - const: gpu_cc_ahb_clk
396 - const: gpu_cc_hlos1_vote_gpu_smmu_clk
397 - const: gpu_cc_cx_gmu_clk
398 - const: gpu_cc_hub_cx_int_clk
399 - const: gpu_cc_hub_aon_clk
403 - description: GPU memnoc_gfx clock
404 - description: GPU snoc_dvm_gfx clock
405 - description: GPU ahb clock
406 - description: GPU hlos1_vote_GPU smmu clock
407 - description: GPU cx_gmu clock
408 - description: GPU hub_cx_int clock
409 - description: GPU hub_aon clock
411 - if:
416 - qcom,sm6350-smmu-v2
417 - qcom,sm7150-smmu-v2
418 - qcom,sm8150-smmu-500
419 - qcom,sm8250-smmu-500
422 clock-names:
424 - const: ahb
425 - const: bus
426 - const: iface
430 - description: bus clock required for AHB bus access
431 - description: bus clock required for downstream bus access and for
433 - description: interface clock required to access smmu's registers
436 - if:
440 - enum:
441 - qcom,sm8350-smmu-500
442 - const: qcom,adreno-smmu
443 - const: qcom,smmu-500
444 - const: arm,mmu-500
447 clock-names:
449 - const: bus
450 - const: iface
451 - const: ahb
452 - const: hlos1_vote_gpu_smmu
453 - const: cx_gmu
454 - const: hub_cx_int
455 - const: hub_aon
460 - if:
464 - enum:
465 - qcom,sm6115-smmu-500
466 - qcom,sm6125-smmu-500
467 - const: qcom,adreno-smmu
468 - const: qcom,smmu-500
469 - const: arm,mmu-500
472 clock-names:
474 - const: mem
475 - const: hlos
476 - const: iface
480 - description: GPU memory bus clock
481 - description: Voter clock required for HLOS SMMU access
482 - description: Interface clock required for register access
484 - if:
487 const: qcom,sm8450-smmu-500
490 clock-names:
492 - const: gmu
493 - const: hub
494 - const: hlos
495 - const: bus
496 - const: iface
497 - const: ahb
501 - description: GMU clock
502 - description: GPU HUB clock
503 - description: HLOS vote clock
504 - description: GPU memory bus clock
505 - description: GPU SNoC bus clock
506 - description: GPU AHB clock
508 - if:
511 const: qcom,sm8550-smmu-500
514 clock-names:
516 - const: hlos
517 - const: bus
518 - const: iface
519 - const: ahb
523 - description: HLOS vote clock
524 - description: GPU memory bus clock
525 - description: GPU SNoC bus clock
526 - description: GPU AHB clock
529 - if:
534 - cavium,smmu-v2
535 - marvell,ap806-smmu-500
536 - nvidia,smmu-500
537 - qcom,qcm2290-smmu-500
538 - qcom,qdu1000-smmu-500
539 - qcom,sc7180-smmu-500
540 - qcom,sc8180x-smmu-500
541 - qcom,sdm670-smmu-500
542 - qcom,sdm845-smmu-500
543 - qcom,sdx55-smmu-500
544 - qcom,sdx65-smmu-500
545 - qcom,sm6350-smmu-500
546 - qcom,sm6375-smmu-500
547 - qcom,sm8650-smmu-500
548 - qcom,x1e80100-smmu-500
551 clock-names: false
554 - if:
558 const: qcom,sm6375-smmu-500
561 power-domains:
563 - description: SNoC MMU TBU RT GDSC
564 - description: SNoC MMU TBU NRT GDSC
565 - description: SNoC TURING MMU TBU0 GDSC
568 - power-domains
571 power-domains:
575 - |+
578 compatible = "arm,smmu-v1";
580 #global-interrupts = <2>;
587 #iommu-cells = <1>;
599 compatible = "arm,smmu-v1";
601 #global-interrupts = <2>;
608 #iommu-cells = <2>;
623 /* ARM MMU-500 with 10-bit stream ID input configuration */
625 compatible = "arm,mmu-500", "arm,smmu-v2";
627 #global-interrupts = <2>;
634 #iommu-cells = <1>;
635 /* always ignore appended 5-bit TBU number */
636 stream-match-mask = <0x7c00>;
640 /* bus whose child devices emit one unique 10-bit stream
642 iommu-map = <0 &smmu3 0 0x400>;
647 - |+
648 /* Qcom's arm,smmu-v2 implementation */
649 #include <dt-bindings/interrupt-controller/arm-gic.h>
650 #include <dt-bindings/interrupt-controller/irq.h>
652 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
655 #global-interrupts = <1>;
659 #iommu-cells = <1>;
660 power-domains = <&mmcc 0>;
664 clock-names = "bus", "iface";