Lines Matching +full:hart +full:- +full:compatible

1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
7 hart contexts in the system, via the external interrupt source in each hart.
9 A hart context is a privilege mode in a hardware execution thread.  For example,
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
11 privilege modes per hart; machine mode and supervisor mode.
13 Each interrupt can be enabled on per-context basis.  Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
28 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
31 - compatible : "sifive,plic-1.0.0" and a string identifying the actual
33 - #address-cells : should be <0> or more.
34 - #interrupt-cells : should be <1> or more.
35 - interrupt-controller : Identifies the node as an interrupt controller.
36 - reg : Should contain 1 register range (address and length).
37 - interrupts-extended : Specifies which contexts are connected to the PLIC,
38   with "-1" specifying that a context is not present.  Each node pointed
39   to should be a riscv,cpu-intc node, which has a riscv node as parent.
40 - riscv,ndev: Specifies how many external interrupts are supported by
45 	plic: interrupt-controller@c000000 {
46 		#address-cells = <0>;
47 		#interrupt-cells = <1>;
48 		compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";
49 		interrupt-controller;
50 		interrupts-extended = <
51 			&cpu0-intc 11
52 			&cpu1-intc 11 &cpu1-intc 9
53 			&cpu2-intc 11 &cpu2-intc 9
54 			&cpu3-intc 11 &cpu3-intc 9
55 			&cpu4-intc 11 &cpu4-intc 9>;