Lines Matching +full:ar7100 +full:- +full:misc +full:- +full:intc

1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8   "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
15 Compatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x,
23 	interrupt-controller@18060010 {
24 		compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
27 		interrupt-parent = <&cpuintc>;
30 		interrupt-controller;
31 		#interrupt-cells = <1>;
36 	interrupt-controller@18060010 {
37 		compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
40 		interrupt-parent = <&cpuintc>;
43 		interrupt-controller;
44 		#interrupt-cells = <1>;