Lines Matching +full:ddr +full:- +full:wb +full:- +full:channels

3 On most SoC the IRQ controller need to flush the DDR FIFO before running
5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
9 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
22 - qca,ddr-wb-channels: List of phandles to the write buffer channels for
23   each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
28 	interrupt-controller {
29 		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";
31 		interrupt-controller;
32 		#interrupt-cells = <1>;
34 		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
35 		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
41 	ddr_ctrl: memory-controller@18000000 {
43 		#qca,ddr-wb-channel-cells = <1>;