Lines Matching +full:gic +full:- +full:timer

1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
4 It also supports local (per-processor) interrupts and software-generated
5 interrupts which can be used as IPIs.  The GIC also includes a free-running
6 global timer, per-CPU count/compare timers, and a watchdog.
9 - compatible : Should be "mti,gic".
10 - interrupt-controller : Identifies the node as an interrupt controller
11 - #interrupt-cells : Specifies the number of cells needed to encode an
13   - The first cell is the type of interrupt, local or shared.
14     See <include/dt-bindings/interrupt-controller/mips-gic.h>.
15   - The second cell is the GIC interrupt number.
16   - The third cell encodes the interrupt flags.
17     See <include/dt-bindings/interrupt-controller/irq.h> for a list of valid
21 - reg : Base address and length of the GIC registers.  If not present,
23 - mti,reserved-cpu-vectors : Specifies the list of CPU interrupt vectors
24   to which the GIC may not route interrupts.  Valid values are 2 - 7.
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
33 Required properties for timer sub-node:
34 - compatible : Should be "mti,gic-timer".
35 - interrupts : Interrupt for the GIC local timer.
37 Optional properties for timer sub-node:
38 - clocks : GIC timer operating clock.
39 - clock-frequency : Clock frequency at which the GIC timers operate.
41 Note that one of clocks or clock-frequency must be specified.
45 	gic: interrupt-controller@1bdc0000 {
46 		compatible = "mti,gic";
49 		interrupt-controller;
50 		#interrupt-cells = <3>;
52 		mti,reserved-cpu-vectors = <7>;
53 		mti,reserved-ipi-vectors = <40 8>;
55 		timer {
56 			compatible = "mti,gic-timer";
58 			clock-frequency = <50000000>;
64 		interrupt-parent = <&gic>;