Lines Matching +full:b +full:- +full:side

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Frank Li <Frank.Li@nxp.com>
16   for one processor (A side) to signal the other processor (B side) using
20   different clocks (from each side of the different peripheral buses).
21   Therefore, the MU must synchronize the accesses from one side to the
23   registers (Processor A-side, Processor B-side).
28   - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33       - fsl,imx6sx-mu-msi
34       - fsl,imx7ulp-mu-msi
35       - fsl,imx8ulp-mu-msi
36       - fsl,imx8ulp-mu-msi-s4
40       - description: a side register base address
41       - description: b side register base address
43   reg-names:
45       - const: processor-a-side
46       - const: processor-b-side
49     description: a side interrupt number.
55   power-domains:
57       - description: a side power domain
58       - description: b side power domain
60   power-domain-names:
62       - const: processor-a-side
63       - const: processor-b-side
65   interrupt-controller: true
67   msi-controller: true
69   "#msi-cells":
73   - compatible
74   - reg
75   - interrupts
76   - interrupt-controller
77   - msi-controller
78   - "#msi-cells"
83   - |
84     #include <dt-bindings/interrupt-controller/arm-gic.h>
85     #include <dt-bindings/firmware/imx/rsrc.h>
87     msi-controller@5d270000 {
88         compatible = "fsl,imx6sx-mu-msi";
89         msi-controller;
90         #msi-cells = <0>;
91         interrupt-controller;
92         reg = <0x5d270000 0x10000>,     /* A side */
93               <0x5d300000 0x10000>;     /* B side */
94         reg-names = "processor-a-side", "processor-b-side";
96         power-domains = <&pd IMX_SC_R_MU_12A>,
98         power-domain-names = "processor-a-side", "processor-b-side";