Lines Matching +full:command +full:- +full:sequencer
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,imx8qxp-dc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Display Controller has a built-in interrupt controller with the following
18 Each interrupt can be connected as IRQ (maskable) and/or NMI (non-maskable).
19 Alternatively the un-masked trigger signals for all HW events are provided,
26 - Liu Ying <victor.liu@nxp.com>
30 const: fsl,imx8qxp-dc-intc
38 interrupt-controller: true
40 "#interrupt-cells":
45 - description: store9 shadow load interrupt(blit engine)
46 - description: store9 frame complete interrupt(blit engine)
47 - description: store9 sequence complete interrupt(blit engine)
48 - description:
51 - description:
54 - description:
57 - description:
60 - description:
63 - description:
66 - description:
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120 - description:
123 - description:
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132 - description:
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138 - description:
141 - description:
144 - description: reserved
145 - description:
146 command sequencer error condition interrupt(command sequencer)
147 - description:
149 - description:
151 - description:
153 - description:
155 - description:
158 - description:
161 - description:
164 - description:
167 - description:
170 - description:
173 - description:
176 - description:
181 interrupt-names:
183 - const: store9_shdload
184 - const: store9_framecomplete
185 - const: store9_seqcomplete
186 - const: extdst0_shdload
187 - const: extdst0_framecomplete
188 - const: extdst0_seqcomplete
189 - const: extdst4_shdload
190 - const: extdst4_framecomplete
191 - const: extdst4_seqcomplete
192 - const: extdst1_shdload
193 - const: extdst1_framecomplete
194 - const: extdst1_seqcomplete
195 - const: extdst5_shdload
196 - const: extdst5_framecomplete
197 - const: extdst5_seqcomplete
198 - const: disengcfg_shdload0
199 - const: disengcfg_framecomplete0
200 - const: disengcfg_seqcomplete0
201 - const: framegen0_int0
202 - const: framegen0_int1
203 - const: framegen0_int2
204 - const: framegen0_int3
205 - const: sig0_shdload
206 - const: sig0_valid
207 - const: sig0_error
208 - const: disengcfg_shdload1
209 - const: disengcfg_framecomplete1
210 - const: disengcfg_seqcomplete1
211 - const: framegen1_int0
212 - const: framegen1_int1
213 - const: framegen1_int2
214 - const: framegen1_int3
215 - const: sig1_shdload
216 - const: sig1_valid
217 - const: sig1_error
218 - const: reserved
219 - const: cmdseq_error
220 - const: comctrl_sw0
221 - const: comctrl_sw1
222 - const: comctrl_sw2
223 - const: comctrl_sw3
224 - const: framegen0_primsync_on
225 - const: framegen0_primsync_off
226 - const: framegen0_secsync_on
227 - const: framegen0_secsync_off
228 - const: framegen1_primsync_on
229 - const: framegen1_primsync_off
230 - const: framegen1_secsync_on
231 - const: framegen1_secsync_off
235 - compatible
236 - reg
237 - clocks
238 - interrupt-controller
239 - "#interrupt-cells"
240 - interrupts
241 - interrupt-names
246 - |
247 #include <dt-bindings/clock/imx8-lpcg.h>
249 interrupt-controller@56180040 {
250 compatible = "fsl,imx8qxp-dc-intc";
253 interrupt-controller;
254 interrupt-parent = <&dc0_irqsteer>;
255 #interrupt-cells = <1>;
269 interrupt-names = "store9_shdload",