Lines Matching +full:t8103 +full:- +full:aic

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Hector Martin <marcan@marcan.st>
19   - Level-triggered hardware IRQs wired to SoC blocks
20     - Single mask bit per IRQ
21     - Per-IRQ affinity setting
22     - Automatic masking on event delivery (auto-ack)
23     - Software triggering (ORed with hw line)
24   - 2 per-CPU IPIs (meant as "self" and "other", but they are interchangeable
26   - Automatic prioritization (single event/ack register per CPU, lower IRQs =
28   - Automatic masking on ack
29   - Default "this CPU" register view and explicit per-CPU views
31   This device also represents the FIQ interrupt sources on platforms using AIC,
35   - $ref: /schemas/interrupt-controller.yaml#
40       - const: apple,t8103-aic
41       - const: apple,aic
43   interrupt-controller: true
45   '#interrupt-cells':
49         - 0: Hardware IRQ
50         - 1: FIQ
53         - HW IRQs: interrupt number
54         - FIQs:
55           - 0: physical HV timer
56           - 1: virtual HV timer
57           - 2: physical guest timer
58           - 3: virtual guest timer
59           - 4: 'efficient' CPU PMU
60           - 5: 'performance' CPU PMU
67       Specifies base physical address and size of the AIC registers.
70   power-domains:
78       containing a set of sub-nodes, one per FIQ with a non-default
81       "^.+-affinity$":
85           apple,fiq-index:
98           - apple,fiq-index
99           - cpus
102   - compatible
103   - '#interrupt-cells'
104   - interrupt-controller
105   - reg
110   - |
112         #address-cells = <2>;
113         #size-cells = <2>;
115         aic: interrupt-controller@23b100000 {
116             compatible = "apple,t8103-aic", "apple,aic";
117             #interrupt-cells = <3>;
118             interrupt-controller;