Lines Matching +full:ppmu +full:- +full:event3 +full:- +full:rightbus
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
18 monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
20 sub-blocks.
22 The Exynos SoC includes the various sub-blocks which have the each AXI bus.
24 line. The power line might be shared among one more sub-blocks. So, we can
25 divide into two type of device as the role of each sub-block. There are two
27 - parent bus device
28 - passive bus device
37 VDD_xxx |--- A block (parent)
38 |--- B block (passive)
39 |--- C block (passive)
42 SoC has different sub-blocks. Therefore, such difference should be specified
46 Detailed correlation between sub-blocks and power line according
48 - In case of Exynos3250, there are two power line as following::
49 VDD_MIF |--- DMC (Dynamic Memory Controller)
51 VDD_INT |--- LEFTBUS (parent device)
52 |--- PERIL
53 |--- MFC
54 |--- G3D
55 |--- RIGHTBUS
56 |--- PERIR
57 |--- FSYS
58 |--- LCD0
59 |--- PERIR
60 |--- ISP
61 |--- CAM
63 - MIF bus's frequency/voltage table
64 -----------------------
66 -----------------------
72 -----------------------
74 - INT bus's frequency/voltage table
75 ----------------------------------------------------------
76 |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP |PERIL ||VDD_INT |
80 ----------------------------------------------------------
82 ----------------------------------------------------------
84 ----------------------------------------------------------
90 ----------------------------------------------------------
92 - In case of Exynos4210, there is one power line as following::
93 VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
94 |--- LEFTBUS
95 |--- PERIL
96 |--- MFC(L)
97 |--- G3D
98 |--- TV
99 |--- LCD0
100 |--- RIGHTBUS
101 |--- PERIR
102 |--- MFC(R)
103 |--- CAM
104 |--- FSYS
105 |--- GPS
106 |--- LCD0
107 |--- LCD1
109 - In case of Exynos4x12, there are two power line as following::
110 VDD_MIF |--- DMC (Dynamic Memory Controller)
112 VDD_INT |--- LEFTBUS (parent device)
113 |--- PERIL
114 |--- MFC(L)
115 |--- G3D
116 |--- TV
117 |--- IMAGE
118 |--- RIGHTBUS
119 |--- PERIR
120 |--- MFC(R)
121 |--- CAM
122 |--- FSYS
123 |--- GPS
124 |--- LCD0
125 |--- ISP
127 - In case of Exynos5422, there are two power line as following::
128 VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
129 |--- DREX 1
131 VDD_INT |--- NoC_Core (parent device)
132 |--- G2D
133 |--- G3D
134 |--- DISP1
135 |--- NoC_WCORE
136 |--- GSCL
137 |--- MSCL
138 |--- ISP
139 |--- MFC
140 |--- GEN
141 |--- PERIS
142 |--- PERIC
143 |--- FSYS
144 |--- FSYS2
146 - In case of Exynos5433, there is VDD_INT power line as following::
147 VDD_INT |--- G2D (parent device)
148 |--- MSCL
149 |--- GSCL
150 |--- JPEG
151 |--- MFC
152 |--- HEVC
153 |--- BUS0
154 |--- BUS1
155 |--- BUS2
156 |--- PERIS (Fixed clock rate)
157 |--- PERIC (Fixed clock rate)
158 |--- FSYS (Fixed clock rate)
163 - samsung,exynos-bus
168 clock-names:
170 - const: bus
177 devfreq-events:
178 $ref: /schemas/types.yaml#/definitions/phandle-array
182 Devfreq-event device to monitor the current utilization of buses. Valid
185 exynos,saturation-ratio:
191 '#interconnect-cells':
198 operating-points-v2: true
199 opp-table:
202 samsung,data-clock-ratio:
209 vdd-supply:
214 - compatible
215 - clocks
216 - clock-names
217 - operating-points-v2
222 - |
223 #include <dt-bindings/clock/exynos3250.h>
225 bus-dmc {
226 compatible = "samsung,exynos-bus";
228 clock-names = "bus";
229 operating-points-v2 = <&bus_dmc_opp_table>;
230 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
231 vdd-supply = <&buck1_reg>;
233 bus_dmc_opp_table: opp-table {
234 compatible = "operating-points-v2";
236 opp-50000000 {
237 opp-hz = /bits/ 64 <50000000>;
238 opp-microvolt = <800000>;
240 opp-100000000 {
241 opp-hz = /bits/ 64 <100000000>;
242 opp-microvolt = <800000>;
244 opp-134000000 {
245 opp-hz = /bits/ 64 <134000000>;
246 opp-microvolt = <800000>;
248 opp-200000000 {
249 opp-hz = /bits/ 64 <200000000>;
250 opp-microvolt = <825000>;
252 opp-400000000 {
253 opp-hz = /bits/ 64 <400000000>;
254 opp-microvolt = <875000>;
259 ppmu_dmc0: ppmu@106a0000 {
260 compatible = "samsung,exynos-ppmu";
263 ppmu_dmc0_3: ppmu-event3-dmc0 {
264 event-name = "ppmu-event3-dmc0";
269 bus_leftbus: bus-leftbus {
270 compatible = "samsung,exynos-bus";
272 clock-names = "bus";
273 operating-points-v2 = <&bus_leftbus_opp_table>;
274 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
275 vdd-supply = <&buck3_reg>;
278 bus-rightbus {
279 compatible = "samsung,exynos-bus";
281 clock-names = "bus";
282 operating-points-v2 = <&bus_leftbus_opp_table>;
286 - |
287 dmc: bus-dmc {
288 compatible = "samsung,exynos-bus";
290 clock-names = "bus";
291 operating-points-v2 = <&bus_dmc_opp_table>;
292 samsung,data-clock-ratio = <4>;
293 #interconnect-cells = <0>;
294 devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
295 vdd-supply = <&buck1_reg>;
298 leftbus: bus-leftbus {
299 compatible = "samsung,exynos-bus";
301 clock-names = "bus";
302 operating-points-v2 = <&bus_leftbus_opp_table>;
304 #interconnect-cells = <0>;
305 devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
306 vdd-supply = <&buck3_reg>;
309 display: bus-display {
310 compatible = "samsung,exynos-bus";
312 clock-names = "bus";
313 operating-points-v2 = <&bus_display_opp_table>;
315 #interconnect-cells = <0>;