Lines Matching +full:opp +full:- +full:specific
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
21 Arteris FlexNOC but DT bindings are specific to the integration of these bus
27 - items:
28 - enum:
29 - fsl,imx8mm-nic
30 - fsl,imx8mn-nic
31 - fsl,imx8mp-nic
32 - fsl,imx8mq-nic
33 - const: fsl,imx8m-nic
34 - items:
35 - enum:
36 - fsl,imx8mm-noc
37 - fsl,imx8mn-noc
38 - fsl,imx8mp-noc
39 - fsl,imx8mq-noc
40 - const: fsl,imx8m-noc
41 - const: fsl,imx8m-nic
49 operating-points-v2: true
50 opp-table:
58 '#interconnect-cells':
65 - compatible
66 - clocks
71 - |
72 #include <dt-bindings/clock/imx8mm-clock.h>
73 #include <dt-bindings/interconnect/imx8mm.h>
74 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc";
80 #interconnect-cells = <1>;
83 operating-points-v2 = <&noc_opp_table>;
84 noc_opp_table: opp-table {
85 compatible = "operating-points-v2";
87 opp-133333333 {
88 opp-hz = /bits/ 64 <133333333>;
90 opp-800000000 {
91 opp-hz = /bits/ 64 <800000000>;
96 ddrc: memory-controller@3d400000 {
97 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
99 clock-names = "core", "pll", "alt", "apb";