Lines Matching +full:channel +full:- +full:select
4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
22 - adi,phase-detector-polarity-positive-enable: Enables positive phase
24 - adi,lock-detect-precision-6ns-enable: Enables 6ns lock detect precision.
26 - adi,lock-detect-function-integer-n-enable: Enables lock detect
27 for integer-N mode. Default = factional-N mode.
28 - adi,charge-pump-current: Charge pump current in mA.
30 - adi,muxout-select: On chip multiplexer output selection.
32 0: Three-State Output (default)
35 3: R-Counter output
36 4: N-Divider output
39 - adi,low-spur-mode-enable: Enables low spur mode.
41 - adi,cycle-slip-reduction-enable: Enables cycle slip reduction.
42 - adi,charge-cancellation-enable: Enabled charge pump
43 charge cancellation for integer-N modes.
44 - adi,anti-backlash-3ns-enable: Enables 3ns antibacklash pulse width
45 for integer-N modes.
46 - adi,band-select-clock-mode-high-enable: Enables faster band
48 - adi,12bit-clk-divider: Clock divider value used when
49 adi,12bit-clkdiv-mode != 0
50 - adi,clk-divider-mode:
55 - adi,aux-output-enable: Enables auxiliary RF output.
56 - adi,aux-output-fundamental-enable: Selects fundamental VCO output on
58 - adi,mute-till-lock-enable: Enables Mute-Till-Lock-Detect function.
59 - adi,output-power: Output power selection.
61 0: -4dBm (default)
62 1: -1dBm
65 - adi,aux-output-power: Auxiliary output power selection.
67 0: -4dBm (default)
68 1: -1dBm
74 lo_pll0_rx_adf4351: adf4351-rx-lpc@4 {
77 spi-max-frequency = <10000000>;
79 clock-names = "clkin";
80 adi,channel-spacing = <10000>;
81 adi,power-up-frequency = <2400000000>;
82 adi,phase-detector-polarity-positive-enable;
83 adi,charge-pump-current = <2500>;
84 adi,output-power = <3>;
85 adi,mute-till-lock-enable;