Lines Matching +full:channel +full:- +full:7

3 This binding document describes the bindings for the Xilinx 7 Series XADC as well
6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
22 	- compatible: Should be one of
23 		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 		* "xlnx,system-management-wiz-1.3": When using the
30 	- reg: Address and length of the register set for the device
31 	- interrupts: Interrupt for the XADC control interface.
32 	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 	  when using the axi-xadc or the axi-system-management-wizard this must be
37 	- xlnx,external-mux:
44 	- xlnx,external-mux-channel: Configures which pair of pins is used to
53 		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
54 		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
56 		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
61 	- xnlx,channels: List of external channels that are connected to the ADC
63 		* #address-cells: Should be 1.
64 		* #size-cells: Should be 0.
70 	  Each child node represents one channel and has the following
73 			* reg: Pair of pins the channel is connected to.
79 			  Note each channel number should only be used at most
82 			* xlnx,bipolar: If set the channel is used in bipolar
88 		compatible = "xlnx,zynq-xadc-1.00.a";
90 		interrupts = <0 7 4>;
91 		interrupt-parent = <&gic>;
95 			#address-cells = <1>;
96 			#size-cells = <0>;
97 			channel@0 {
100 			channel@1 {
103 			channel@8 {
110 		compatible = "xlnx,axi-xadc-1.00.a";
113 		interrupt-parent = <&gic>;
117 			#address-cells = <1>;
118 			#size-cells = <0>;
119 			channel@0 {
127 		compatible = "xlnx,system-management-wiz-1.3";
130 		interrupt-parent = <&gic>;
134 			#address-cells = <1>;
135 			#size-cells = <0>;
136 			channel@0 {