Lines Matching +full:pins +full:- +full:sda +full:- +full:scl
4 - compatible : Must be one of:
5 "atmel,at91rm9200-i2c",
6 "atmel,at91sam9261-i2c",
7 "atmel,at91sam9260-i2c",
8 "atmel,at91sam9g20-i2c",
9 "atmel,at91sam9g10-i2c",
10 "atmel,at91sam9x5-i2c",
11 "atmel,sama5d4-i2c",
12 "atmel,sama5d2-i2c",
13 "microchip,sam9x60-i2c".
14 - reg: physical base address of the controller and length of memory mapped
16 - interrupts: interrupt number to the cpu.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - clocks: phandles to input clocks.
22 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
23 - dmas: A list of two dma specifiers, one for each entry in dma-names.
24 - dma-names: should contain "tx" and "rx".
25 - atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
27 - i2c-sda-hold-time-ns: TWD hold time, only available for:
28 "atmel,sama5d4-i2c",
29 "atmel,sama5d2-i2c",
30 "microchip,sam9x60-i2c".
31 - scl-gpios: specify the gpio related to SCL pin
32 - sda-gpios: specify the gpio related to SDA pin
33 - pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
35 - Child nodes conforming to i2c bus binding
41 compatible = "atmel,at91sam9g20-i2c";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 clock-frequency = <400000>;
57 compatible = "atmel,sama5d2-i2c";
66 dma-names = "tx", "rx";
67 #address-cells = <1>;
68 #size-cells = <0>;
70 atmel,fifo-size = <16>;
71 i2c-sda-hold-time-ns = <336>;
72 pinctrl-names = "default", "gpio";
73 pinctrl-0 = <&pinctrl_i2c0>;
74 pinctrl-1 = <&pinctrl_i2c0_gpio>;
75 sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
76 scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;