Lines Matching +full:tegra210 +full:- +full:host1x
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 NVENC is the hardware video encoder present on NVIDIA Tegra210
11 and newer chips. It is located on the Host1x bus and typically
12 programmed through Host1x channels.
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
34 clock-names:
36 - const: nvenc
41 reset-names:
43 - const: nvenc
45 power-domains:
51 dma-coherent: true
57 interconnect-names:
61 nvidia,host1x-class:
63 Host1x class of the engine, used to specify the targeted engine
64 when programming the engine through Host1x channels or when
65 configuring engine-specific behavior in Host1x.
70 - compatible
71 - reg
72 - clocks
73 - clock-names
74 - resets
75 - reset-names
76 - power-domains
79 - if:
83 - nvidia,tegra210-nvenc
84 - nvidia,tegra186-nvenc
89 - description: DMA read memory client
90 - description: DMA write memory client
91 interconnect-names:
93 - const: dma-mem
94 - const: write
95 - if:
99 - nvidia,tegra194-nvenc
104 - description: DMA read memory client
105 - description: DMA read 2 memory client
106 - description: DMA write memory client
107 interconnect-names:
109 - const: dma-mem
110 - const: read-1
111 - const: write
116 - |
117 #include <dt-bindings/clock/tegra186-clock.h>
118 #include <dt-bindings/memory/tegra186-mc.h>
119 #include <dt-bindings/power/tegra186-powergate.h>
120 #include <dt-bindings/reset/tegra186-reset.h>
123 compatible = "nvidia,tegra186-nvenc";
126 clock-names = "nvenc";
128 reset-names = "nvenc";
130 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
133 interconnect-names = "dma-mem", "write";