Lines Matching +full:tegra210 +full:- +full:host1x

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   NVDEC is the hardware video decoder present on NVIDIA Tegra210
11   and newer chips. It is located on the Host1x bus and typically
12   programmed through Host1x channels.
15   - Thierry Reding <treding@gmail.com>
16   - Mikko Perttunen <mperttunen@nvidia.com>
20     pattern: "^nvdec@[0-9a-f]*$"
24       - nvidia,tegra210-nvdec
25       - nvidia,tegra186-nvdec
26       - nvidia,tegra194-nvdec
34   clock-names:
36       - const: nvdec
41   reset-names:
43       - const: nvdec
45   power-domains:
51   dma-coherent: true
55       - description: DMA read memory client
56       - description: DMA read 2 memory client
57       - description: DMA write memory client
59   interconnect-names:
61       - const: dma-mem
62       - const: read-1
63       - const: write
65   nvidia,host1x-class:
67       Host1x class of the engine, used to specify the targeted engine
68       when programming the engine through Host1x channels or when
69       configuring engine-specific behavior in Host1x.
74   - compatible
75   - reg
76   - clocks
77   - clock-names
78   - resets
79   - reset-names
80   - power-domains
85   - |
86     #include <dt-bindings/clock/tegra186-clock.h>
87     #include <dt-bindings/interrupt-controller/arm-gic.h>
88     #include <dt-bindings/memory/tegra186-mc.h>
89     #include <dt-bindings/power/tegra186-powergate.h>
90     #include <dt-bindings/reset/tegra186-reset.h>
93             compatible = "nvidia,tegra186-nvdec";
96             clock-names = "nvdec";
98             reset-names = "nvdec";
100             power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
104             interconnect-names = "dma-mem", "read-1", "write";