Lines Matching +full:per +full:- +full:port +full:- +full:set

9 The Tegra186 GPIO controller allows software to set the IO direction of, and
15 register set. These registers exist in a single contiguous block of physical
19 Access to this set of registers is not necessary in all circumstances. Code
31 implemented by the SoC. Each GPIO is assigned to a port, and a port may control
32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
33 name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
37 implemented GPIOs within each port varies. GPIO registers within a controller
38 are grouped and laid out according to the port they affect.
40 The mapping from port name to the GPIO controller that implements that port, and
41 the mapping from port name to register offset within a controller, are both
42 extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
43 describes the port-level mapping. In that file, the naming convention for ports
49 represents the aggregate status for all GPIOs within a set of ports. Thus, the
52 both the overall controller HW module and the sets-of-ports as "controllers".
54 Each GPIO controller in fact generates multiple interrupts signals for each set
56 interrupt signals generated by a set-of-ports. The intent is for each generated
58 handle subsets of the interrupts within a port. The status of each of these
59 per-port-set signals is reported via a separate register. Thus, a driver needs
62 GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
66 - compatible
69     - "nvidia,tegra186-gpio".
70     - "nvidia,tegra186-gpio-aon".
71     - "nvidia,tegra194-gpio".
72     - "nvidia,tegra194-gpio-aon".
73 - reg-names
77     - "gpio": Mandatory. GPIO control registers. This may cover either:
82     - "security": Optional. Security configuration registers.
84     using this reg-names property to do so.
85 - reg
87     Must contain one entry per entry in the reg-names property, in a matching
89 - interrupts
91     The interrupt outputs from the HW block, one per set of ports, in the
94     - "nvidia,tegra186-gpio": 6 entries.
95     - "nvidia,tegra186-gpio-aon": 1 entry.
96     - "nvidia,tegra194-gpio": 6 entries.
97     - "nvidia,tegra194-gpio-aon": 1 entry.
98 - gpio-controller
101 - #gpio-cells
102     Single-cell integer.
106     - The first cell is the pin number.
107         See <dt-bindings/gpio/tegra186-gpio.h>.
108     - The second cell contains flags:
109         - Bit 0 specifies polarity
110             - 0: Active-high (normal).
111             - 1: Active-low (inverted).
112 - interrupt-controller
115 - #interrupt-cells
116     Single-cell integer.
120     - The first cell is the GPIO number.
121         See <dt-bindings/gpio/tegra186-gpio.h>.
122     - The second cell is contains flags:
123         - Bits [3:0] indicate trigger type and level:
124             - 1: Low-to-high edge triggered.
125             - 2: High-to-low edge triggered.
126             - 4: Active high level-sensitive.
127             - 8: Active low level-sensitive.
132 #include <dt-bindings/interrupt-controller/irq.h>
135 	compatible = "nvidia,tegra186-gpio";
136 	reg-names = "security", "gpio";
147 	gpio-controller;
148 	#gpio-cells = <2>;
149 	interrupt-controller;
150 	#interrupt-cells = <2>;
154 	compatible = "nvidia,tegra186-gpio-aon";
155 	reg-names = "security", "gpio";
161 	gpio-controller;
162 	#gpio-cells = <2>;
163 	interrupt-controller;
164 	#interrupt-cells = <2>;