Lines Matching +full:non +full:- +full:probeable
4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
32 fsi-slave-engine@<addr> {
39 Note that since the bus is probe-able, some (or all) of the topology may
44 -----------
46 FSI master nodes declare themselves as such with the "fsi-master" compatible
47 value. It's likely that an implementation-specific compatible value will
50 compatible = "fsi-master-gpio", "fsi-master";
52 Since the master nodes describe the top-level of the FSI topology, they also
53 need to declare the FSI-standard addressing scheme. This requires two cells for
56 #address-cells = <2>;
57 #size-cells = <0>;
64 no-scan-on-init;
67 ----------
69 Slaves are identified by a (link-index, slave-id) pair, so require two cells
79 Each slave provides an address-space, under which the engines are accessible.
83 #address-cells = <1>;
84 #size-cells = <1>;
89 chip-id = <0>;
92 ---------------------
96 FSI device, and are passed to those FSI device drivers' ->probe() functions.
98 For example, for a slave using a single 0x400-byte page starting at address
107 ------------
110 - an FSI master
111 - connected to an FSI slave
112 - that contains an engine that is an I2C master
113 - connected to an I2C EEPROM
119 /* The GPIO-based FSI master node, describing the top level of the
122 gpio-fsi {
123 compatible = "fsi-master-gpio", "fsi-master";
124 #address-cells = <2>;
125 #size-cells = <0>;
130 #address-cells = <1>;
131 #size-cells = <1>;
132 chip-id = <0>;
138 i2c-controller@c00 {
141 /* Engine-specific data. In this case, we're describing an
144 compatible = "some-vendor,fsi-i2c-controller";
145 #address-cells = <1>;
146 #size-cells = <1>;