Lines Matching +full:full +full:- +full:bridge
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
18 - Supported Use Models
19 - Constraints
38 Full Reconfiguration
64 FPGA Bridge
69 * During Full Reconfiguration, hardware bridges between the host and FPGA
71 * During Partial Reconfiguration of a specific region, that region's bridge
77 own bridge and its own split of the busses in the FPGA.
85 * An FPGA image that is designed to do full reconfiguration of the FPGA.
89 ---------------- ----------------------------------
92 | ----| | ----------- -------- |
94 | | W | | | ----------- -------- |
96 | | B |<=====>|<==| ----------- -------- |
98 | | I | | | ----------- -------- |
100 | | G | | | ----------- -------- |
102 | ----| | ----------- -------- |
104 ---------------- ----------------------------------
107 region (PRR0-2) gets its own split of the busses that is independently gated by
108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
137 * image-specific information needed to the programming.
144 If the live tree shows a "firmware-name" property or child nodes under an FPGA
146 and adds the "firmware-name" property is taken as a request to reprogram the
150 The base FPGA Region in the device tree represents the FPGA and supports full
152 FPGA region will be the child of one of the hardware bridges (the bridge that
154 one bridge to control during FPGA programming, the region will also contain a
159 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
183 bridges behind the scenes. No FPGA Bridge devices are needed for full
186 * Full reconfiguration with hardware bridges
188 need to be controlled during full reconfiguration. Before the overlay is
190 FPGA Region. The FPGA Region is the child of the bridge that allows
192 fpga-bridges property in the FPGA region or in the device tree overlay.
217 --
218 [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf
224 pattern: "^fpga-region(@.*|-([0-9]|[1-9][0-9]+))?$"
227 const: fpga-region
233 "#address-cells": true
234 "#size-cells": true
236 config-complete-timeout-us:
241 encrypted-fpga-config:
246 external-fpga-config:
251 firmware-name:
260 fpga-bridges:
261 $ref: /schemas/types.yaml#/definitions/phandle-array
264 controlled during FPGA programming along with the parent FPGA bridge.
266 If the fpga-region is the child of an fpga-bridge, the list should not
267 contain the parent bridge.
269 fpga-mgr:
273 inherit this property from their ancestor regions. An fpga-mgr property
276 partial-fpga-config:
279 Set if partial reconfiguration is to be done, otherwise full
282 region-freeze-timeout-us:
287 region-unfreeze-timeout-us:
293 - compatible
294 - fpga-mgr
300 - |
302 * Full Reconfiguration without Bridges with DT overlay
304 fpga_region0: fpga-region@0 {
305 compatible = "fpga-region";
307 #address-cells = <1>;
308 #size-cells = <1>;
309 fpga-mgr = <&fpga_mgr0>;
313 firmware-name = "zynq-gpio.bin";
315 compatible = "xlnx,xps-gpio-1.00.a";
317 gpio-controller;
318 #gpio-cells = <2>;
323 - |
325 * Partial reconfiguration with bridge
327 fpga_region1: fpga-region@0 {
328 compatible = "fpga-region";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 fpga-mgr = <&fpga_mgr1>;
334 fpga-bridges = <&fpga_bridge1>;
335 partial-fpga-config;
338 firmware-name = "zynq-gpio-partial.bin";
340 compatible = "fixed-factor-clock";
342 #clock-cells = <0>;
343 clock-div = <2>;
344 clock-mult = <1>;
347 compatible = "simple-bus";
348 #address-cells = <1>;
349 #size-cells = <1>;
352 compatible = "xlnx,xps-gpio-1.00.a";
354 #gpio-cells = <2>;
355 gpio-controller;