Lines Matching +full:pm +full:- +full:api

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
23       - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24         const: xlnx,zynqmp-firmware
26       - description: For implementations complying for Versal.
27         const: xlnx,versal-firmware
31                  The method of calling the PM-API firmware layer.
33                  - "smc" : SMC #0, following the SMCCC
34                  - "hvc" : HVC #0, following the SMCCC
36     $ref: /schemas/types.yaml#/definitions/string-array
38       - smc
39       - hvc
41   "#power-domain-cells":
45     $ref: /schemas/fpga/xlnx,versal-fpga.yaml#
49   zynqmp-aes:
50     $ref: /schemas/crypto/xlnx,zynqmp-aes.yaml#
51     description: The ZynqMP AES-GCM hardened cryptographic accelerator is
56   clock-controller:
57     $ref: /schemas/clock/xlnx,versal-clk.yaml#
66   - compatible
71   - |
72     #include <dt-bindings/power/xlnx-zynqmp-power.h>
74       zynqmp_firmware: zynqmp-firmware {
75         #power-domain-cells = <1>;
80       power-domains = <&zynqmp_firmware PD_SATA>;
83     versal-firmware {
84       compatible = "xlnx,versal-firmware";
88         compatible = "xlnx,versal-fpga";
91       xlnx_aes: zynqmp-aes {
92         compatible = "xlnx,zynqmp-aes";
95       versal_clk: clock-controller {
96         #clock-cells = <1>;
97         compatible = "xlnx,versal-clk";
99         clock-names = "ref", "pl_alt_ref";