Lines Matching +full:power +full:- +full:domain +full:- +full:node

1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
4 booting process handling and offloading the power management, clock
11 - compatible
14     - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
18 - #clock-cells : Should be 1.
19 - #power-domain-cells : Should be 1.
20 - #reset-cells : Should be 1.
22 This node is a mailbox consumer. See the following files for details of
26 - .../mailbox/mailbox.txt
27 - .../mailbox/nvidia,tegra186-hsp.txt
29 This node is a clock, power domain, and reset provider. See the following
31 implemented by this node:
33 - .../clock/clock-bindings.txt
34 - <dt-bindings/clock/tegra186-clock.h>
35 - ../power/power-domain.yaml
36 - <dt-bindings/power/tegra186-powergate.h>
37 - .../reset/reset.txt
38 - <dt-bindings/reset/tegra186-reset.h>
42 bindings represent each I2C controller as a device tree node. Such nodes should
43 be nested directly inside the main BPMP node.
45 Software can determine whether a child node of the BPMP node represents a device
46 by checking for a compatible property. Any node with a compatible property
52 The BPMP firmware defines no single global name-/numbering-space for such
56 property, and the BPMP node will have no #address-cells or #size-cells property.
59 -----------------------------------
70 	#mbox-cells = <2>;
74 	compatible = "nvidia,tegra186-sysram", "mmio-sram";
76 	#address-cells = <2>;
77 	#size-cells = <2>;
81 		compatible = "nvidia,tegra186-bpmp-shmem";
83 		label = "cpu-bpmp-tx";
88 		compatible = "nvidia,tegra186-bpmp-shmem";
90 		label = "cpu-bpmp-rx";
96 	compatible = "nvidia,tegra186-bpmp";
99 	#clock-cells = <1>;
100 	#power-domain-cells = <1>;
101 	#reset-cells = <1>;