Lines Matching +full:cpu +full:- +full:bpmp +full:- +full:tx
1 NVIDIA Tegra Boot and Power Management Processor (BPMP)
3 The BPMP is a specific processor in Tegra chip, which is designed for
5 management, and reset control tasks from the CPU. The binding document
6 defines the resources that would be used by the BPMP firmware driver,
7 which can create the interprocessor communication (IPC) between the CPU
8 and BPMP.
11 - compatible
14 - "nvidia,tegra186-bpmp"
15 - mboxes : The phandle of mailbox controller and the mailbox specifier.
16 - shmem : List of the phandle of the TX and RX shared memory area that
17 the IPC between CPU and BPMP is based on.
18 - #clock-cells : Should be 1.
19 - #power-domain-cells : Should be 1.
20 - #reset-cells : Should be 1.
26 - .../mailbox/mailbox.txt
27 - .../mailbox/nvidia,tegra186-hsp.txt
33 - .../clock/clock-bindings.txt
34 - <dt-bindings/clock/tegra186-clock.h>
35 - ../power/power-domain.yaml
36 - <dt-bindings/power/tegra186-powergate.h>
37 - .../reset/reset.txt
38 - <dt-bindings/reset/tegra186-reset.h>
40 The BPMP implements some services which must be represented by separate nodes.
43 be nested directly inside the main BPMP node.
45 Software can determine whether a child node of the BPMP node represents a device
48 property may be used to provide configuration information regarding the BPMP
52 The BPMP firmware defines no single global name-/numbering-space for such
54 the numbering scheme for any other service the BPMP may provide (e.g. a future
56 property, and the BPMP node will have no #address-cells or #size-cells property.
58 The shared memory bindings for BPMP
59 -----------------------------------
61 The shared memory area for the IPC TX and RX between CPU and BPMP are
70 #mbox-cells = <2>;
74 compatible = "nvidia,tegra186-sysram", "mmio-sram";
76 #address-cells = <2>;
77 #size-cells = <2>;
81 compatible = "nvidia,tegra186-bpmp-shmem";
83 label = "cpu-bpmp-tx";
88 compatible = "nvidia,tegra186-bpmp-shmem";
90 label = "cpu-bpmp-rx";
95 bpmp {
96 compatible = "nvidia,tegra186-bpmp";
99 #clock-cells = <1>;
100 #power-domain-cells = <1>;
101 #reset-cells = <1>;