Lines Matching +full:imx8qxp +full:- +full:sc +full:- +full:gpio
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
19 5 remote AP connections to the SC to support up to 5 execution environments
20 (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
21 with the LSIO DSC IP bus. The SC firmware will communicate with this MU
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
33 gpio:
35 Control the GPIO PINs on SCU domain over the firmware APIs
36 $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml
41 $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
46 $ref: /schemas/input/fsl,scu-key.yaml
53 channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
56 instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
60 - items:
61 - description: TX0 MU channel
62 - description: RX0 MU channel
63 - items:
64 - description: TX0 MU channel
65 - description: RX0 MU channel
66 - description: optional MU channel for general interrupt
67 - items:
68 - description: TX0 MU channel
69 - description: TX1 MU channel
70 - description: TX2 MU channel
71 - description: TX3 MU channel
72 - description: RX0 MU channel
73 - description: RX1 MU channel
74 - description: RX2 MU channel
75 - description: RX3 MU channel
76 - items:
77 - description: TX0 MU channel
78 - description: TX1 MU channel
79 - description: TX2 MU channel
80 - description: TX3 MU channel
81 - description: RX0 MU channel
82 - description: RX1 MU channel
83 - description: RX2 MU channel
84 - description: RX3 MU channel
85 - description: optional MU channel for general interrupt
87 mbox-names:
89 - items:
90 - const: tx0
91 - const: rx0
92 - items:
93 - const: tx0
94 - const: rx0
95 - const: gip3
96 - items:
97 - const: tx0
98 - const: tx1
99 - const: tx2
100 - const: tx3
101 - const: rx0
102 - const: rx1
103 - const: rx2
104 - const: rx3
105 - items:
106 - const: tx0
107 - const: tx1
108 - const: tx2
109 - const: tx3
110 - const: rx0
111 - const: rx1
112 - const: rx2
113 - const: rx3
114 - const: gip3
119 $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
121 power-controller:
125 $ref: /schemas/power/fsl,scu-pd.yaml
130 $ref: /schemas/rtc/fsl,scu-rtc.yaml
132 thermal-sensor:
135 $ref: /schemas/thermal/fsl,scu-thermal.yaml
140 $ref: /schemas/watchdog/fsl,scu-wdt.yaml
143 - compatible
144 - mbox-names
145 - mboxes
150 - |
151 #include <dt-bindings/firmware/imx/rsrc.h>
152 #include <dt-bindings/input/input.h>
153 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
156 system-controller {
157 compatible = "fsl,imx-scu";
158 mbox-names = "tx0", "tx1", "tx2", "tx3",
165 clock-controller {
166 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
167 #clock-cells = <2>;
171 compatible = "fsl,imx8qxp-iomuxc";
182 compatible = "fsl,imx8qxp-scu-ocotp";
183 #address-cells = <1>;
184 #size-cells = <1>;
191 power-controller {
192 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
193 #power-domain-cells = <1>;
197 compatible = "fsl,imx8qxp-sc-rtc";
201 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
206 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
207 timeout-sec = <60>;
210 thermal-sensor {
211 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
212 #thermal-sensor-cells = <1>;