Lines Matching +full:zynqmp +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DMA Engine
10 The Xilinx ZynqMP DMA engine supports memory to memory transfers,
15 - Michael Tretter <m.tretter@pengutronix.de>
16 - Harini Katakam <harini.katakam@amd.com>
17 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
20 - $ref: ../dma-controller.yaml#
23 "#dma-cells":
27 const: xlnx,zynqmp-dma-1.0
42 clock-names:
44 - const: clk_main
45 - const: clk_apb
47 xlnx,bus-width:
50 - 64
51 - 128
57 power-domains:
60 dma-coherent:
64 - "#dma-cells"
65 - compatible
66 - reg
67 - interrupts
68 - clocks
69 - clock-names
70 - xlnx,bus-width
75 - |
76 #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
78 fpd_dma_chan1: dma-controller@fd500000 {
79 compatible = "xlnx,zynqmp-dma-1.0";
81 interrupt-parent = <&gic>;
83 #dma-cells = <1>;
84 clock-names = "clk_main", "clk_apb";
86 xlnx,bus-width = <128>;
87 dma-coherent;