Lines Matching +full:0 +full:x40400000

61         -bit 0-1: The priority level
62           0x0: low priority, low weight
63           0x1: low priority, mid weight
64           0x2: low priority, high weight
65           0x3: high priority
67           0x0: no FIFO requirement/any channel can fit
68           0x2: FIFO of 8 bytes (2^2+1)
69           0x4: FIFO of 32 bytes (2^4+1)
70           0x6: FIFO of 128 bytes (2^6+1)
71           0x7: FIFO of 256 bytes (2^7+1)
73         -bit 0: The source incrementing burst
74           0x0: fixed burst
75           0x1: contiguously incremented burst
77           0x0: port 0 is allocated to the source transfer
78           0x1: port 1 is allocated to the source transfer
80           0x0: fixed burst
81           0x1: contiguously incremented burst
83           0x0: port 0 is allocated to the destination transfer
84           0x1: port 1 is allocated to the destination transfer
86           0x0: burst
87           0x1: block
89           0x0: DMA controller control mode
90           0x1: peripheral control mode
92           0x0: at block level, transfer complete event is generated at the end
94           0x2: at LLI level, the transfer complete event is generated at the end
97           0x3: at channel level, the transfer complete event is generated at the
115       reg = <0x40400000 0x1000>;