Lines Matching +full:multi +full:- +full:master
4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
14 increase from chan n->0
15 - block_size: Maximum block size supported by the controller
16 - data-width: Maximum data width supported by hardware per AHB master
21 - data_width: Maximum data width supported by hardware per AHB master
22 (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
26 - multi-block: Multi block transfers supported by hardware. Array property with
28 - snps,dma-protection-control: AHB HPROT[3:1] protection setting.
29 The default value is 0 (for non-cacheable, non-buffered,
31 Refer to include/dt-bindings/dma/dw-dmac.h for possible values.
36 compatible = "snps,dma-spear1340";
38 interrupt-parent = <&vic1>;
41 dma-channels = <8>;
42 dma-requests = <16>;
43 dma-masters = <2>;
44 #dma-cells = <3>;
48 data-width = <8 8>;
52 described in the dma.txt file, using a four-cell specifier for each channel.
57 3. Memory master for transfers on allocated channel
58 4. Peripheral master for transfers on allocated channel
68 dma-names = "rx", "rx";