Lines Matching +full:ch3 +full:- +full:0

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Biju Das <biju.das.jz@bp.renesas.com>
13   - $ref: dma-controller.yaml#
18       - enum:
19           - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
20           - renesas,r9a07g044-dmac # RZ/G2{L,LC}
21           - renesas,r9a07g054-dmac # RZ/V2L
22       - const: renesas,rz-dmac
26       - description: Control and channel register block
27       - description: DMA extended resource selector block
32   interrupt-names:
34       - const: error
35       - const: ch0
36       - const: ch1
37       - const: ch2
38       - const: ch3
39       - const: ch4
40       - const: ch5
41       - const: ch6
42       - const: ch7
43       - const: ch8
44       - const: ch9
45       - const: ch10
46       - const: ch11
47       - const: ch12
48       - const: ch13
49       - const: ch14
50       - const: ch15
54       - description: DMA main clock
55       - description: DMA register access clock
57   clock-names:
59       - const: main
60       - const: register
62   '#dma-cells':
68       bits[0:9] - Specifies MID/RID value
69       bit[10] - Specifies DMA request high enable (HIEN)
70       bit[11] - Specifies DMA request detection type (LVL)
71       bits[12:14] - Specifies DMAACK output mode (AM)
72       bit[15] - Specifies Transfer Mode (TM)
74   dma-channels:
77   power-domains:
82       - description: Reset for DMA ARESETN reset terminal
83       - description: Reset for DMA RST_ASYNC reset terminal
85   reset-names:
87       - const: arst
88       - const: rst_async
91   - compatible
92   - reg
93   - interrupts
94   - interrupt-names
95   - clocks
96   - clock-names
97   - '#dma-cells'
98   - dma-channels
99   - power-domains
100   - resets
101   - reset-names
106   - |
107     #include <dt-bindings/interrupt-controller/arm-gic.h>
108     #include <dt-bindings/clock/r9a07g044-cpg.h>
110     dmac: dma-controller@11820000 {
111         compatible = "renesas,r9a07g044-dmac",
112                      "renesas,rz-dmac";
113         reg = <0x11820000 0x10000>,
114               <0x11830000 0x10000>;
132         interrupt-names = "error",
133                           "ch0", "ch1", "ch2", "ch3",
139         clock-names = "main", "register";
140         power-domains = <&cpg>;
143         reset-names = "arst", "rst_async";
144         #dma-cells = <1>;
145         dma-channels = <16>;