Lines Matching +full:imx35 +full:- +full:sdma

1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
4 - compatible : Should be one of
5       "fsl,imx25-sdma"
6       "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7       "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
8       "fsl,imx51-sdma"
9       "fsl,imx53-sdma"
10       "fsl,imx6q-sdma"
11       "fsl,imx7d-sdma"
12       "fsl,imx6ul-sdma"
13       "fsl,imx8mq-sdma"
14       "fsl,imx8mm-sdma"
15       "fsl,imx8mn-sdma"
16       "fsl,imx8mp-sdma"
17   The -to variants should be preferred since they allow to determine the
20 - reg : Should contain SDMA registers location and length
21 - interrupts : Should contain SDMA interrupt
22 - #dma-cells : Must be <3>.
25 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
32 	---------------------
62 	-------------------------
69 - gpr : The phandle to the General Purpose Register (GPR) node.
70 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
78 sdma@83fb0000 {
79 	compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
82 	#dma-cells = <3>;
83 	fsl,sdma-ram-script-name = "sdma-imx51.bin";
86 DMA clients connected to the i.MX SDMA controller must use the format
92 	compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
96 	dmas = <&sdma 24 1 0>,
97 	       <&sdma 25 1 0>;
98 	dma-names = "rx", "tx";
99 	fsl,fifo-depth = <15>;
102 Using the fsl,sdma-event-remap property:
104 If we want to use SDMA on the SAI1 port on a MX6SX:
106 &sdma {
108 	/* SDMA events remap for SAI1_RX and SAI1_TX */
109 	fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
112 The fsl,sdma-event-remap property in this case has two values:
113 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
114 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
116 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
117 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.